162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree file for LaCie 2Big NAS
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2015 Seagate
662306a36Sopenharmony_ci *
762306a36Sopenharmony_ci * Author: Simon Guinot <simon.guinot@sequanux.org>
862306a36Sopenharmony_ci *
962306a36Sopenharmony_ci*/
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci/dts-v1/;
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#include "kirkwood-netxbig.dtsi"
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci/ {
1662306a36Sopenharmony_ci	model = "LaCie 2Big NAS";
1762306a36Sopenharmony_ci	compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood";
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci	memory {
2062306a36Sopenharmony_ci		device_type = "memory";
2162306a36Sopenharmony_ci		reg = <0x00000000 0x10000000>;
2262306a36Sopenharmony_ci	};
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci	chosen {
2562306a36Sopenharmony_ci		bootargs = "console=ttyS0,115200n8";
2662306a36Sopenharmony_ci		stdout-path = &uart0;
2762306a36Sopenharmony_ci	};
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci	ocp@f1000000 {
3062306a36Sopenharmony_ci		rtc@10300 {
3162306a36Sopenharmony_ci			/* The on-chip RTC is not powered (no supercap). */
3262306a36Sopenharmony_ci			status = "disabled";
3362306a36Sopenharmony_ci		};
3462306a36Sopenharmony_ci		spi@10600 {
3562306a36Sopenharmony_ci			/*
3662306a36Sopenharmony_ci			 * A NAND flash is used instead of an SPI flash for
3762306a36Sopenharmony_ci			 * the other netxbig-compatible boards.
3862306a36Sopenharmony_ci			 */
3962306a36Sopenharmony_ci			status = "disabled";
4062306a36Sopenharmony_ci		};
4162306a36Sopenharmony_ci	};
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci	fan {
4462306a36Sopenharmony_ci		/*
4562306a36Sopenharmony_ci		 * An I2C fan controller (GMT G762) is used but alarm is
4662306a36Sopenharmony_ci		 * wired to a separate GPIO.
4762306a36Sopenharmony_ci		 */
4862306a36Sopenharmony_ci		compatible = "gpio-fan";
4962306a36Sopenharmony_ci		alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
5062306a36Sopenharmony_ci	};
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci	regulators: regulators {
5362306a36Sopenharmony_ci		status = "okay";
5462306a36Sopenharmony_ci		compatible = "simple-bus";
5562306a36Sopenharmony_ci		#address-cells = <1>;
5662306a36Sopenharmony_ci		#size-cells = <0>;
5762306a36Sopenharmony_ci		pinctrl-names = "default";
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ci		regulator@2 {
6062306a36Sopenharmony_ci			compatible = "regulator-fixed";
6162306a36Sopenharmony_ci			reg = <2>;
6262306a36Sopenharmony_ci			regulator-name = "hdd1power";
6362306a36Sopenharmony_ci			regulator-min-microvolt = <5000000>;
6462306a36Sopenharmony_ci			regulator-max-microvolt = <5000000>;
6562306a36Sopenharmony_ci			enable-active-high;
6662306a36Sopenharmony_ci			regulator-always-on;
6762306a36Sopenharmony_ci			regulator-boot-on;
6862306a36Sopenharmony_ci			gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
6962306a36Sopenharmony_ci		};
7062306a36Sopenharmony_ci		clocks {
7162306a36Sopenharmony_ci			g762_clk: g762-oscillator {
7262306a36Sopenharmony_ci				compatible = "fixed-clock";
7362306a36Sopenharmony_ci				#clock-cells = <0>;
7462306a36Sopenharmony_ci				clock-frequency = <32768>;
7562306a36Sopenharmony_ci			};
7662306a36Sopenharmony_ci		};
7762306a36Sopenharmony_ci	};
7862306a36Sopenharmony_ci};
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci&mdio {
8162306a36Sopenharmony_ci	status = "okay";
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci	ethphy0: ethernet-phy@0 {
8462306a36Sopenharmony_ci		reg = <0>;
8562306a36Sopenharmony_ci	};
8662306a36Sopenharmony_ci};
8762306a36Sopenharmony_ci
8862306a36Sopenharmony_ci&i2c0 {
8962306a36Sopenharmony_ci	status = "okay";
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_ci	/*
9262306a36Sopenharmony_ci	 * An external I2C RTC (Dallas DS1337S+) is used. This allows
9362306a36Sopenharmony_ci	 * to power-up the board on an RTC alarm. The external RTC can
9462306a36Sopenharmony_ci	 * be kept powered, even when the SoC is off.
9562306a36Sopenharmony_ci	 */
9662306a36Sopenharmony_ci	rtc@68 {
9762306a36Sopenharmony_ci		compatible = "dallas,ds1307";
9862306a36Sopenharmony_ci		reg = <0x68>;
9962306a36Sopenharmony_ci		interrupts = <43>;
10062306a36Sopenharmony_ci	};
10162306a36Sopenharmony_ci	g762@3e {
10262306a36Sopenharmony_ci		compatible = "gmt,g762";
10362306a36Sopenharmony_ci		reg = <0x3e>;
10462306a36Sopenharmony_ci		clocks = <&g762_clk>;
10562306a36Sopenharmony_ci	};
10662306a36Sopenharmony_ci};
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_ci&nand {
10962306a36Sopenharmony_ci	chip-delay = <50>;
11062306a36Sopenharmony_ci	status = "okay";
11162306a36Sopenharmony_ci
11262306a36Sopenharmony_ci	partition@0 {
11362306a36Sopenharmony_ci		label = "U-Boot";
11462306a36Sopenharmony_ci		reg = <0x0 0x100000>;
11562306a36Sopenharmony_ci	};
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ci	partition@100000 {
11862306a36Sopenharmony_ci		label = "uImage";
11962306a36Sopenharmony_ci		reg = <0x100000 0x1000000>;
12062306a36Sopenharmony_ci	};
12162306a36Sopenharmony_ci
12262306a36Sopenharmony_ci	partition@1100000 {
12362306a36Sopenharmony_ci		label = "root";
12462306a36Sopenharmony_ci		reg = <0x1100000 0x8000000>;
12562306a36Sopenharmony_ci	};
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ci	partition@9100000 {
12862306a36Sopenharmony_ci		label = "unused";
12962306a36Sopenharmony_ci		reg = <0x9100000 0x6f00000>;
13062306a36Sopenharmony_ci	};
13162306a36Sopenharmony_ci};
13262306a36Sopenharmony_ci
13362306a36Sopenharmony_ci&pciec {
13462306a36Sopenharmony_ci	status = "okay";
13562306a36Sopenharmony_ci};
13662306a36Sopenharmony_ci
13762306a36Sopenharmony_ci&pcie0 {
13862306a36Sopenharmony_ci	status = "okay";
13962306a36Sopenharmony_ci};
140