162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci/ { 362306a36Sopenharmony_ci mbus@f1000000 { 462306a36Sopenharmony_ci pciec: pcie@82000000 { 562306a36Sopenharmony_ci compatible = "marvell,kirkwood-pcie"; 662306a36Sopenharmony_ci status = "disabled"; 762306a36Sopenharmony_ci device_type = "pci"; 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci #address-cells = <3>; 1062306a36Sopenharmony_ci #size-cells = <2>; 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci bus-range = <0x00 0xff>; 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci ranges = 1562306a36Sopenharmony_ci <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 1662306a36Sopenharmony_ci 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 1762306a36Sopenharmony_ci 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 1862306a36Sopenharmony_ci 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 1962306a36Sopenharmony_ci 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 2062306a36Sopenharmony_ci 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 2162306a36Sopenharmony_ci 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci pcie0: pcie@1,0 { 2462306a36Sopenharmony_ci device_type = "pci"; 2562306a36Sopenharmony_ci assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 2662306a36Sopenharmony_ci reg = <0x0800 0 0 0 0>; 2762306a36Sopenharmony_ci #address-cells = <3>; 2862306a36Sopenharmony_ci #size-cells = <2>; 2962306a36Sopenharmony_ci #interrupt-cells = <1>; 3062306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 3162306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x1 0 1 0>; 3262306a36Sopenharmony_ci bus-range = <0x00 0xff>; 3362306a36Sopenharmony_ci interrupt-names = "intx", "error"; 3462306a36Sopenharmony_ci interrupts = <9>, <44>; 3562306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 3662306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie0_intc 0>, 3762306a36Sopenharmony_ci <0 0 0 2 &pcie0_intc 1>, 3862306a36Sopenharmony_ci <0 0 0 3 &pcie0_intc 2>, 3962306a36Sopenharmony_ci <0 0 0 4 &pcie0_intc 3>; 4062306a36Sopenharmony_ci marvell,pcie-port = <0>; 4162306a36Sopenharmony_ci marvell,pcie-lane = <0>; 4262306a36Sopenharmony_ci clocks = <&gate_clk 2>; 4362306a36Sopenharmony_ci status = "disabled"; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci pcie0_intc: interrupt-controller { 4662306a36Sopenharmony_ci interrupt-controller; 4762306a36Sopenharmony_ci #interrupt-cells = <1>; 4862306a36Sopenharmony_ci }; 4962306a36Sopenharmony_ci }; 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci pcie1: pcie@2,0 { 5262306a36Sopenharmony_ci device_type = "pci"; 5362306a36Sopenharmony_ci assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; 5462306a36Sopenharmony_ci reg = <0x1000 0 0 0 0>; 5562306a36Sopenharmony_ci #address-cells = <3>; 5662306a36Sopenharmony_ci #size-cells = <2>; 5762306a36Sopenharmony_ci #interrupt-cells = <1>; 5862306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 5962306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x2 0 1 0>; 6062306a36Sopenharmony_ci bus-range = <0x00 0xff>; 6162306a36Sopenharmony_ci interrupt-names = "intx", "error"; 6262306a36Sopenharmony_ci interrupts = <10>, <45>; 6362306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 6462306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie1_intc 0>, 6562306a36Sopenharmony_ci <0 0 0 2 &pcie1_intc 1>, 6662306a36Sopenharmony_ci <0 0 0 3 &pcie1_intc 2>, 6762306a36Sopenharmony_ci <0 0 0 4 &pcie1_intc 3>; 6862306a36Sopenharmony_ci marvell,pcie-port = <1>; 6962306a36Sopenharmony_ci marvell,pcie-lane = <0>; 7062306a36Sopenharmony_ci clocks = <&gate_clk 18>; 7162306a36Sopenharmony_ci status = "disabled"; 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci pcie1_intc: interrupt-controller { 7462306a36Sopenharmony_ci interrupt-controller; 7562306a36Sopenharmony_ci #interrupt-cells = <1>; 7662306a36Sopenharmony_ci }; 7762306a36Sopenharmony_ci }; 7862306a36Sopenharmony_ci }; 7962306a36Sopenharmony_ci }; 8062306a36Sopenharmony_ci ocp@f1000000 { 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci pinctrl: pin-controller@10000 { 8362306a36Sopenharmony_ci compatible = "marvell,88f6282-pinctrl"; 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci pmx_sata0: pmx-sata0 { 8662306a36Sopenharmony_ci marvell,pins = "mpp5", "mpp21", "mpp23"; 8762306a36Sopenharmony_ci marvell,function = "sata0"; 8862306a36Sopenharmony_ci }; 8962306a36Sopenharmony_ci pmx_sata1: pmx-sata1 { 9062306a36Sopenharmony_ci marvell,pins = "mpp4", "mpp20", "mpp22"; 9162306a36Sopenharmony_ci marvell,function = "sata1"; 9262306a36Sopenharmony_ci }; 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ci /* 9562306a36Sopenharmony_ci * Default I2C1 pinctrl setting on mpp36/mpp37, 9662306a36Sopenharmony_ci * overwrite marvell,pins on board level if required. 9762306a36Sopenharmony_ci */ 9862306a36Sopenharmony_ci pmx_twsi1: pmx-twsi1 { 9962306a36Sopenharmony_ci marvell,pins = "mpp36", "mpp37"; 10062306a36Sopenharmony_ci marvell,function = "twsi1"; 10162306a36Sopenharmony_ci }; 10262306a36Sopenharmony_ci 10362306a36Sopenharmony_ci pmx_sdio: pmx-sdio { 10462306a36Sopenharmony_ci marvell,pins = "mpp12", "mpp13", "mpp14", 10562306a36Sopenharmony_ci "mpp15", "mpp16", "mpp17"; 10662306a36Sopenharmony_ci marvell,function = "sdio"; 10762306a36Sopenharmony_ci }; 10862306a36Sopenharmony_ci }; 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_ci thermal: thermal@10078 { 11162306a36Sopenharmony_ci compatible = "marvell,kirkwood-thermal"; 11262306a36Sopenharmony_ci reg = <0x10078 0x4>; 11362306a36Sopenharmony_ci status = "okay"; 11462306a36Sopenharmony_ci }; 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ci rtc: rtc@10300 { 11762306a36Sopenharmony_ci compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 11862306a36Sopenharmony_ci reg = <0x10300 0x20>; 11962306a36Sopenharmony_ci interrupts = <53>; 12062306a36Sopenharmony_ci clocks = <&gate_clk 7>; 12162306a36Sopenharmony_ci }; 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci i2c1: i2c@11100 { 12462306a36Sopenharmony_ci compatible = "marvell,mv64xxx-i2c"; 12562306a36Sopenharmony_ci reg = <0x11100 0x20>; 12662306a36Sopenharmony_ci #address-cells = <1>; 12762306a36Sopenharmony_ci #size-cells = <0>; 12862306a36Sopenharmony_ci interrupts = <32>; 12962306a36Sopenharmony_ci clock-frequency = <100000>; 13062306a36Sopenharmony_ci clocks = <&gate_clk 7>; 13162306a36Sopenharmony_ci pinctrl-0 = <&pmx_twsi1>; 13262306a36Sopenharmony_ci pinctrl-names = "default"; 13362306a36Sopenharmony_ci status = "disabled"; 13462306a36Sopenharmony_ci }; 13562306a36Sopenharmony_ci 13662306a36Sopenharmony_ci sata: sata@80000 { 13762306a36Sopenharmony_ci compatible = "marvell,orion-sata"; 13862306a36Sopenharmony_ci reg = <0x80000 0x5000>; 13962306a36Sopenharmony_ci interrupts = <21>; 14062306a36Sopenharmony_ci clocks = <&gate_clk 14>, <&gate_clk 15>; 14162306a36Sopenharmony_ci clock-names = "0", "1"; 14262306a36Sopenharmony_ci phys = <&sata_phy0>, <&sata_phy1>; 14362306a36Sopenharmony_ci phy-names = "port0", "port1"; 14462306a36Sopenharmony_ci status = "disabled"; 14562306a36Sopenharmony_ci }; 14662306a36Sopenharmony_ci 14762306a36Sopenharmony_ci sdio: mvsdio@90000 { 14862306a36Sopenharmony_ci compatible = "marvell,orion-sdio"; 14962306a36Sopenharmony_ci reg = <0x90000 0x200>; 15062306a36Sopenharmony_ci interrupts = <28>; 15162306a36Sopenharmony_ci clocks = <&gate_clk 4>; 15262306a36Sopenharmony_ci pinctrl-0 = <&pmx_sdio>; 15362306a36Sopenharmony_ci pinctrl-names = "default"; 15462306a36Sopenharmony_ci bus-width = <4>; 15562306a36Sopenharmony_ci cap-sdio-irq; 15662306a36Sopenharmony_ci cap-sd-highspeed; 15762306a36Sopenharmony_ci cap-mmc-highspeed; 15862306a36Sopenharmony_ci status = "disabled"; 15962306a36Sopenharmony_ci }; 16062306a36Sopenharmony_ci }; 16162306a36Sopenharmony_ci}; 162