162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Device Tree Include file for Marvell Armada XP family SoC 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2012 Marvell 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 862306a36Sopenharmony_ci * 962306a36Sopenharmony_ci * Contains definitions specific to the Armada XP MV78260 SoC that are not 1062306a36Sopenharmony_ci * common to all Armada XP SoCs. 1162306a36Sopenharmony_ci */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#include "armada-xp.dtsi" 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci/ { 1662306a36Sopenharmony_ci model = "Marvell Armada XP MV78260 SoC"; 1762306a36Sopenharmony_ci compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci aliases { 2062306a36Sopenharmony_ci gpio0 = &gpio0; 2162306a36Sopenharmony_ci gpio1 = &gpio1; 2262306a36Sopenharmony_ci gpio2 = &gpio2; 2362306a36Sopenharmony_ci }; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci cpus { 2662306a36Sopenharmony_ci #address-cells = <1>; 2762306a36Sopenharmony_ci #size-cells = <0>; 2862306a36Sopenharmony_ci enable-method = "marvell,armada-xp-smp"; 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci cpu@0 { 3162306a36Sopenharmony_ci device_type = "cpu"; 3262306a36Sopenharmony_ci compatible = "marvell,sheeva-v7"; 3362306a36Sopenharmony_ci reg = <0>; 3462306a36Sopenharmony_ci clocks = <&cpuclk 0>; 3562306a36Sopenharmony_ci clock-latency = <1000000>; 3662306a36Sopenharmony_ci }; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci cpu@1 { 3962306a36Sopenharmony_ci device_type = "cpu"; 4062306a36Sopenharmony_ci compatible = "marvell,sheeva-v7"; 4162306a36Sopenharmony_ci reg = <1>; 4262306a36Sopenharmony_ci clocks = <&cpuclk 1>; 4362306a36Sopenharmony_ci clock-latency = <1000000>; 4462306a36Sopenharmony_ci }; 4562306a36Sopenharmony_ci }; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci soc { 4862306a36Sopenharmony_ci /* 4962306a36Sopenharmony_ci * MV78260 has 3 PCIe units Gen2.0: Two units can be 5062306a36Sopenharmony_ci * configured as x4 or quad x1 lanes. One unit is 5162306a36Sopenharmony_ci * x4 only. 5262306a36Sopenharmony_ci */ 5362306a36Sopenharmony_ci pciec: pcie@82000000 { 5462306a36Sopenharmony_ci compatible = "marvell,armada-xp-pcie"; 5562306a36Sopenharmony_ci status = "disabled"; 5662306a36Sopenharmony_ci device_type = "pci"; 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci #address-cells = <3>; 5962306a36Sopenharmony_ci #size-cells = <2>; 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci msi-parent = <&mpic>; 6262306a36Sopenharmony_ci bus-range = <0x00 0xff>; 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci ranges = 6562306a36Sopenharmony_ci <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 6662306a36Sopenharmony_ci 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 6762306a36Sopenharmony_ci 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 6862306a36Sopenharmony_ci 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 6962306a36Sopenharmony_ci 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 7062306a36Sopenharmony_ci 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 7162306a36Sopenharmony_ci 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 7262306a36Sopenharmony_ci 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 7362306a36Sopenharmony_ci 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 7462306a36Sopenharmony_ci 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 7562306a36Sopenharmony_ci 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 7662306a36Sopenharmony_ci 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 7762306a36Sopenharmony_ci 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 7862306a36Sopenharmony_ci 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 7962306a36Sopenharmony_ci 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 8062306a36Sopenharmony_ci 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 8162306a36Sopenharmony_ci 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ci 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 8462306a36Sopenharmony_ci 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 8562306a36Sopenharmony_ci 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 8662306a36Sopenharmony_ci 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 8762306a36Sopenharmony_ci 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 8862306a36Sopenharmony_ci 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 8962306a36Sopenharmony_ci 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 9062306a36Sopenharmony_ci 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 9162306a36Sopenharmony_ci 9262306a36Sopenharmony_ci 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 9362306a36Sopenharmony_ci 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 9462306a36Sopenharmony_ci 9562306a36Sopenharmony_ci pcie1: pcie@1,0 { 9662306a36Sopenharmony_ci device_type = "pci"; 9762306a36Sopenharmony_ci assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 9862306a36Sopenharmony_ci reg = <0x0800 0 0 0 0>; 9962306a36Sopenharmony_ci #address-cells = <3>; 10062306a36Sopenharmony_ci #size-cells = <2>; 10162306a36Sopenharmony_ci interrupt-names = "intx"; 10262306a36Sopenharmony_ci interrupts-extended = <&mpic 58>; 10362306a36Sopenharmony_ci #interrupt-cells = <1>; 10462306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 10562306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x1 0 1 0>; 10662306a36Sopenharmony_ci bus-range = <0x00 0xff>; 10762306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 10862306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie1_intc 0>, 10962306a36Sopenharmony_ci <0 0 0 2 &pcie1_intc 1>, 11062306a36Sopenharmony_ci <0 0 0 3 &pcie1_intc 2>, 11162306a36Sopenharmony_ci <0 0 0 4 &pcie1_intc 3>; 11262306a36Sopenharmony_ci marvell,pcie-port = <0>; 11362306a36Sopenharmony_ci marvell,pcie-lane = <0>; 11462306a36Sopenharmony_ci clocks = <&gateclk 5>; 11562306a36Sopenharmony_ci status = "disabled"; 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_ci pcie1_intc: interrupt-controller { 11862306a36Sopenharmony_ci interrupt-controller; 11962306a36Sopenharmony_ci #interrupt-cells = <1>; 12062306a36Sopenharmony_ci }; 12162306a36Sopenharmony_ci }; 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci pcie2: pcie@2,0 { 12462306a36Sopenharmony_ci device_type = "pci"; 12562306a36Sopenharmony_ci assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 12662306a36Sopenharmony_ci reg = <0x1000 0 0 0 0>; 12762306a36Sopenharmony_ci #address-cells = <3>; 12862306a36Sopenharmony_ci #size-cells = <2>; 12962306a36Sopenharmony_ci interrupt-names = "intx"; 13062306a36Sopenharmony_ci interrupts-extended = <&mpic 59>; 13162306a36Sopenharmony_ci #interrupt-cells = <1>; 13262306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 13362306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x2 0 1 0>; 13462306a36Sopenharmony_ci bus-range = <0x00 0xff>; 13562306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 13662306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie2_intc 0>, 13762306a36Sopenharmony_ci <0 0 0 2 &pcie2_intc 1>, 13862306a36Sopenharmony_ci <0 0 0 3 &pcie2_intc 2>, 13962306a36Sopenharmony_ci <0 0 0 4 &pcie2_intc 3>; 14062306a36Sopenharmony_ci marvell,pcie-port = <0>; 14162306a36Sopenharmony_ci marvell,pcie-lane = <1>; 14262306a36Sopenharmony_ci clocks = <&gateclk 6>; 14362306a36Sopenharmony_ci status = "disabled"; 14462306a36Sopenharmony_ci 14562306a36Sopenharmony_ci pcie2_intc: interrupt-controller { 14662306a36Sopenharmony_ci interrupt-controller; 14762306a36Sopenharmony_ci #interrupt-cells = <1>; 14862306a36Sopenharmony_ci }; 14962306a36Sopenharmony_ci }; 15062306a36Sopenharmony_ci 15162306a36Sopenharmony_ci pcie3: pcie@3,0 { 15262306a36Sopenharmony_ci device_type = "pci"; 15362306a36Sopenharmony_ci assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 15462306a36Sopenharmony_ci reg = <0x1800 0 0 0 0>; 15562306a36Sopenharmony_ci #address-cells = <3>; 15662306a36Sopenharmony_ci #size-cells = <2>; 15762306a36Sopenharmony_ci interrupt-names = "intx"; 15862306a36Sopenharmony_ci interrupts-extended = <&mpic 60>; 15962306a36Sopenharmony_ci #interrupt-cells = <1>; 16062306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 16162306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x3 0 1 0>; 16262306a36Sopenharmony_ci bus-range = <0x00 0xff>; 16362306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 16462306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie3_intc 0>, 16562306a36Sopenharmony_ci <0 0 0 2 &pcie3_intc 1>, 16662306a36Sopenharmony_ci <0 0 0 3 &pcie3_intc 2>, 16762306a36Sopenharmony_ci <0 0 0 4 &pcie3_intc 3>; 16862306a36Sopenharmony_ci marvell,pcie-port = <0>; 16962306a36Sopenharmony_ci marvell,pcie-lane = <2>; 17062306a36Sopenharmony_ci clocks = <&gateclk 7>; 17162306a36Sopenharmony_ci status = "disabled"; 17262306a36Sopenharmony_ci 17362306a36Sopenharmony_ci pcie3_intc: interrupt-controller { 17462306a36Sopenharmony_ci interrupt-controller; 17562306a36Sopenharmony_ci #interrupt-cells = <1>; 17662306a36Sopenharmony_ci }; 17762306a36Sopenharmony_ci }; 17862306a36Sopenharmony_ci 17962306a36Sopenharmony_ci pcie4: pcie@4,0 { 18062306a36Sopenharmony_ci device_type = "pci"; 18162306a36Sopenharmony_ci assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 18262306a36Sopenharmony_ci reg = <0x2000 0 0 0 0>; 18362306a36Sopenharmony_ci #address-cells = <3>; 18462306a36Sopenharmony_ci #size-cells = <2>; 18562306a36Sopenharmony_ci interrupt-names = "intx"; 18662306a36Sopenharmony_ci interrupts-extended = <&mpic 61>; 18762306a36Sopenharmony_ci #interrupt-cells = <1>; 18862306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 18962306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x4 0 1 0>; 19062306a36Sopenharmony_ci bus-range = <0x00 0xff>; 19162306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 19262306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie4_intc 0>, 19362306a36Sopenharmony_ci <0 0 0 2 &pcie4_intc 1>, 19462306a36Sopenharmony_ci <0 0 0 3 &pcie4_intc 2>, 19562306a36Sopenharmony_ci <0 0 0 4 &pcie4_intc 3>; 19662306a36Sopenharmony_ci marvell,pcie-port = <0>; 19762306a36Sopenharmony_ci marvell,pcie-lane = <3>; 19862306a36Sopenharmony_ci clocks = <&gateclk 8>; 19962306a36Sopenharmony_ci status = "disabled"; 20062306a36Sopenharmony_ci 20162306a36Sopenharmony_ci pcie4_intc: interrupt-controller { 20262306a36Sopenharmony_ci interrupt-controller; 20362306a36Sopenharmony_ci #interrupt-cells = <1>; 20462306a36Sopenharmony_ci }; 20562306a36Sopenharmony_ci }; 20662306a36Sopenharmony_ci 20762306a36Sopenharmony_ci pcie5: pcie@5,0 { 20862306a36Sopenharmony_ci device_type = "pci"; 20962306a36Sopenharmony_ci assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 21062306a36Sopenharmony_ci reg = <0x2800 0 0 0 0>; 21162306a36Sopenharmony_ci #address-cells = <3>; 21262306a36Sopenharmony_ci #size-cells = <2>; 21362306a36Sopenharmony_ci interrupt-names = "intx"; 21462306a36Sopenharmony_ci interrupts-extended = <&mpic 62>; 21562306a36Sopenharmony_ci #interrupt-cells = <1>; 21662306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 21762306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x5 0 1 0>; 21862306a36Sopenharmony_ci bus-range = <0x00 0xff>; 21962306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 22062306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie5_intc 0>, 22162306a36Sopenharmony_ci <0 0 0 2 &pcie5_intc 1>, 22262306a36Sopenharmony_ci <0 0 0 3 &pcie5_intc 2>, 22362306a36Sopenharmony_ci <0 0 0 4 &pcie5_intc 3>; 22462306a36Sopenharmony_ci marvell,pcie-port = <1>; 22562306a36Sopenharmony_ci marvell,pcie-lane = <0>; 22662306a36Sopenharmony_ci clocks = <&gateclk 9>; 22762306a36Sopenharmony_ci status = "disabled"; 22862306a36Sopenharmony_ci 22962306a36Sopenharmony_ci pcie5_intc: interrupt-controller { 23062306a36Sopenharmony_ci interrupt-controller; 23162306a36Sopenharmony_ci #interrupt-cells = <1>; 23262306a36Sopenharmony_ci }; 23362306a36Sopenharmony_ci }; 23462306a36Sopenharmony_ci 23562306a36Sopenharmony_ci pcie6: pcie@6,0 { 23662306a36Sopenharmony_ci device_type = "pci"; 23762306a36Sopenharmony_ci assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 23862306a36Sopenharmony_ci reg = <0x3000 0 0 0 0>; 23962306a36Sopenharmony_ci #address-cells = <3>; 24062306a36Sopenharmony_ci #size-cells = <2>; 24162306a36Sopenharmony_ci interrupt-names = "intx"; 24262306a36Sopenharmony_ci interrupts-extended = <&mpic 63>; 24362306a36Sopenharmony_ci #interrupt-cells = <1>; 24462306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 24562306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x6 0 1 0>; 24662306a36Sopenharmony_ci bus-range = <0x00 0xff>; 24762306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 24862306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie6_intc 0>, 24962306a36Sopenharmony_ci <0 0 0 2 &pcie6_intc 1>, 25062306a36Sopenharmony_ci <0 0 0 3 &pcie6_intc 2>, 25162306a36Sopenharmony_ci <0 0 0 4 &pcie6_intc 3>; 25262306a36Sopenharmony_ci marvell,pcie-port = <1>; 25362306a36Sopenharmony_ci marvell,pcie-lane = <1>; 25462306a36Sopenharmony_ci clocks = <&gateclk 10>; 25562306a36Sopenharmony_ci status = "disabled"; 25662306a36Sopenharmony_ci 25762306a36Sopenharmony_ci pcie6_intc: interrupt-controller { 25862306a36Sopenharmony_ci interrupt-controller; 25962306a36Sopenharmony_ci #interrupt-cells = <1>; 26062306a36Sopenharmony_ci }; 26162306a36Sopenharmony_ci }; 26262306a36Sopenharmony_ci 26362306a36Sopenharmony_ci pcie7: pcie@7,0 { 26462306a36Sopenharmony_ci device_type = "pci"; 26562306a36Sopenharmony_ci assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 26662306a36Sopenharmony_ci reg = <0x3800 0 0 0 0>; 26762306a36Sopenharmony_ci #address-cells = <3>; 26862306a36Sopenharmony_ci #size-cells = <2>; 26962306a36Sopenharmony_ci interrupt-names = "intx"; 27062306a36Sopenharmony_ci interrupts-extended = <&mpic 64>; 27162306a36Sopenharmony_ci #interrupt-cells = <1>; 27262306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 27362306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x7 0 1 0>; 27462306a36Sopenharmony_ci bus-range = <0x00 0xff>; 27562306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 27662306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie7_intc 0>, 27762306a36Sopenharmony_ci <0 0 0 2 &pcie7_intc 1>, 27862306a36Sopenharmony_ci <0 0 0 3 &pcie7_intc 2>, 27962306a36Sopenharmony_ci <0 0 0 4 &pcie7_intc 3>; 28062306a36Sopenharmony_ci marvell,pcie-port = <1>; 28162306a36Sopenharmony_ci marvell,pcie-lane = <2>; 28262306a36Sopenharmony_ci clocks = <&gateclk 11>; 28362306a36Sopenharmony_ci status = "disabled"; 28462306a36Sopenharmony_ci 28562306a36Sopenharmony_ci pcie7_intc: interrupt-controller { 28662306a36Sopenharmony_ci interrupt-controller; 28762306a36Sopenharmony_ci #interrupt-cells = <1>; 28862306a36Sopenharmony_ci }; 28962306a36Sopenharmony_ci }; 29062306a36Sopenharmony_ci 29162306a36Sopenharmony_ci pcie8: pcie@8,0 { 29262306a36Sopenharmony_ci device_type = "pci"; 29362306a36Sopenharmony_ci assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 29462306a36Sopenharmony_ci reg = <0x4000 0 0 0 0>; 29562306a36Sopenharmony_ci #address-cells = <3>; 29662306a36Sopenharmony_ci #size-cells = <2>; 29762306a36Sopenharmony_ci interrupt-names = "intx"; 29862306a36Sopenharmony_ci interrupts-extended = <&mpic 65>; 29962306a36Sopenharmony_ci #interrupt-cells = <1>; 30062306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 30162306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x8 0 1 0>; 30262306a36Sopenharmony_ci bus-range = <0x00 0xff>; 30362306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 30462306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie8_intc 0>, 30562306a36Sopenharmony_ci <0 0 0 2 &pcie8_intc 1>, 30662306a36Sopenharmony_ci <0 0 0 3 &pcie8_intc 2>, 30762306a36Sopenharmony_ci <0 0 0 4 &pcie8_intc 3>; 30862306a36Sopenharmony_ci marvell,pcie-port = <1>; 30962306a36Sopenharmony_ci marvell,pcie-lane = <3>; 31062306a36Sopenharmony_ci clocks = <&gateclk 12>; 31162306a36Sopenharmony_ci status = "disabled"; 31262306a36Sopenharmony_ci 31362306a36Sopenharmony_ci pcie8_intc: interrupt-controller { 31462306a36Sopenharmony_ci interrupt-controller; 31562306a36Sopenharmony_ci #interrupt-cells = <1>; 31662306a36Sopenharmony_ci }; 31762306a36Sopenharmony_ci }; 31862306a36Sopenharmony_ci 31962306a36Sopenharmony_ci pcie9: pcie@9,0 { 32062306a36Sopenharmony_ci device_type = "pci"; 32162306a36Sopenharmony_ci assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 32262306a36Sopenharmony_ci reg = <0x4800 0 0 0 0>; 32362306a36Sopenharmony_ci #address-cells = <3>; 32462306a36Sopenharmony_ci #size-cells = <2>; 32562306a36Sopenharmony_ci interrupt-names = "intx"; 32662306a36Sopenharmony_ci interrupts-extended = <&mpic 99>; 32762306a36Sopenharmony_ci #interrupt-cells = <1>; 32862306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 32962306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x9 0 1 0>; 33062306a36Sopenharmony_ci bus-range = <0x00 0xff>; 33162306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 33262306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie9_intc 0>, 33362306a36Sopenharmony_ci <0 0 0 2 &pcie9_intc 1>, 33462306a36Sopenharmony_ci <0 0 0 3 &pcie9_intc 2>, 33562306a36Sopenharmony_ci <0 0 0 4 &pcie9_intc 3>; 33662306a36Sopenharmony_ci marvell,pcie-port = <2>; 33762306a36Sopenharmony_ci marvell,pcie-lane = <0>; 33862306a36Sopenharmony_ci clocks = <&gateclk 26>; 33962306a36Sopenharmony_ci status = "disabled"; 34062306a36Sopenharmony_ci 34162306a36Sopenharmony_ci pcie9_intc: interrupt-controller { 34262306a36Sopenharmony_ci interrupt-controller; 34362306a36Sopenharmony_ci #interrupt-cells = <1>; 34462306a36Sopenharmony_ci }; 34562306a36Sopenharmony_ci }; 34662306a36Sopenharmony_ci }; 34762306a36Sopenharmony_ci 34862306a36Sopenharmony_ci internal-regs { 34962306a36Sopenharmony_ci gpio0: gpio@18100 { 35062306a36Sopenharmony_ci compatible = "marvell,armada-370-gpio", 35162306a36Sopenharmony_ci "marvell,orion-gpio"; 35262306a36Sopenharmony_ci reg = <0x18100 0x40>, <0x181c0 0x08>; 35362306a36Sopenharmony_ci reg-names = "gpio", "pwm"; 35462306a36Sopenharmony_ci ngpios = <32>; 35562306a36Sopenharmony_ci gpio-controller; 35662306a36Sopenharmony_ci #gpio-cells = <2>; 35762306a36Sopenharmony_ci #pwm-cells = <2>; 35862306a36Sopenharmony_ci interrupt-controller; 35962306a36Sopenharmony_ci #interrupt-cells = <2>; 36062306a36Sopenharmony_ci interrupts = <82>, <83>, <84>, <85>; 36162306a36Sopenharmony_ci clocks = <&coreclk 0>; 36262306a36Sopenharmony_ci }; 36362306a36Sopenharmony_ci 36462306a36Sopenharmony_ci gpio1: gpio@18140 { 36562306a36Sopenharmony_ci compatible = "marvell,armada-370-gpio", 36662306a36Sopenharmony_ci "marvell,orion-gpio"; 36762306a36Sopenharmony_ci reg = <0x18140 0x40>, <0x181c8 0x08>; 36862306a36Sopenharmony_ci reg-names = "gpio", "pwm"; 36962306a36Sopenharmony_ci ngpios = <32>; 37062306a36Sopenharmony_ci gpio-controller; 37162306a36Sopenharmony_ci #gpio-cells = <2>; 37262306a36Sopenharmony_ci #pwm-cells = <2>; 37362306a36Sopenharmony_ci interrupt-controller; 37462306a36Sopenharmony_ci #interrupt-cells = <2>; 37562306a36Sopenharmony_ci interrupts = <87>, <88>, <89>, <90>; 37662306a36Sopenharmony_ci clocks = <&coreclk 0>; 37762306a36Sopenharmony_ci }; 37862306a36Sopenharmony_ci 37962306a36Sopenharmony_ci gpio2: gpio@18180 { 38062306a36Sopenharmony_ci compatible = "marvell,armada-370-gpio", 38162306a36Sopenharmony_ci "marvell,orion-gpio"; 38262306a36Sopenharmony_ci reg = <0x18180 0x40>; 38362306a36Sopenharmony_ci ngpios = <3>; 38462306a36Sopenharmony_ci gpio-controller; 38562306a36Sopenharmony_ci #gpio-cells = <2>; 38662306a36Sopenharmony_ci interrupt-controller; 38762306a36Sopenharmony_ci #interrupt-cells = <2>; 38862306a36Sopenharmony_ci interrupts = <91>; 38962306a36Sopenharmony_ci }; 39062306a36Sopenharmony_ci 39162306a36Sopenharmony_ci eth3: ethernet@34000 { 39262306a36Sopenharmony_ci compatible = "marvell,armada-xp-neta"; 39362306a36Sopenharmony_ci reg = <0x34000 0x4000>; 39462306a36Sopenharmony_ci interrupts = <14>; 39562306a36Sopenharmony_ci clocks = <&gateclk 1>; 39662306a36Sopenharmony_ci status = "disabled"; 39762306a36Sopenharmony_ci }; 39862306a36Sopenharmony_ci }; 39962306a36Sopenharmony_ci }; 40062306a36Sopenharmony_ci}; 40162306a36Sopenharmony_ci 40262306a36Sopenharmony_ci&pinctrl { 40362306a36Sopenharmony_ci compatible = "marvell,mv78260-pinctrl"; 40462306a36Sopenharmony_ci}; 405