162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree file for Marvell Armada XP development board
462306a36Sopenharmony_ci * (DB-MV784MP-GP)
562306a36Sopenharmony_ci *
662306a36Sopenharmony_ci * Copyright (C) 2013-2014 Marvell
762306a36Sopenharmony_ci *
862306a36Sopenharmony_ci * Lior Amsalem <alior@marvell.com>
962306a36Sopenharmony_ci * Gregory CLEMENT <gregory.clement@free-electrons.com>
1062306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
1162306a36Sopenharmony_ci *
1262306a36Sopenharmony_ci * Note: this Device Tree assumes that the bootloader has remapped the
1362306a36Sopenharmony_ci * internal registers to 0xf1000000 (instead of the default
1462306a36Sopenharmony_ci * 0xd0000000). The 0xf1000000 is the default used by the recent,
1562306a36Sopenharmony_ci * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
1662306a36Sopenharmony_ci * boards were delivered with an older version of the bootloader that
1762306a36Sopenharmony_ci * left internal registers mapped at 0xd0000000. If you are in this
1862306a36Sopenharmony_ci * situation, you should either update your bootloader (preferred
1962306a36Sopenharmony_ci * solution) or the below Device Tree should be adjusted.
2062306a36Sopenharmony_ci */
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci/dts-v1/;
2362306a36Sopenharmony_ci#include <dt-bindings/gpio/gpio.h>
2462306a36Sopenharmony_ci#include "armada-xp-mv78460.dtsi"
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ci/ {
2762306a36Sopenharmony_ci	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
2862306a36Sopenharmony_ci	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci	chosen {
3162306a36Sopenharmony_ci		stdout-path = "serial0:115200n8";
3262306a36Sopenharmony_ci	};
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci	memory@0 {
3562306a36Sopenharmony_ci		device_type = "memory";
3662306a36Sopenharmony_ci		/*
3762306a36Sopenharmony_ci                 * 8 GB of plug-in RAM modules by default.The amount
3862306a36Sopenharmony_ci                 * of memory available can be changed by the
3962306a36Sopenharmony_ci                 * bootloader according the size of the module
4062306a36Sopenharmony_ci                 * actually plugged. However, memory between
4162306a36Sopenharmony_ci                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
4262306a36Sopenharmony_ci                 * the address range used for I/O (internal registers,
4362306a36Sopenharmony_ci                 * MBus windows).
4462306a36Sopenharmony_ci		 */
4562306a36Sopenharmony_ci		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
4662306a36Sopenharmony_ci		      <0x00000001 0x00000000 0x00000001 0x00000000>;
4762306a36Sopenharmony_ci	};
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_ci	cpus {
5062306a36Sopenharmony_ci		pm_pic {
5162306a36Sopenharmony_ci			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
5262306a36Sopenharmony_ci				     <&gpio0 17 GPIO_ACTIVE_LOW>,
5362306a36Sopenharmony_ci				     <&gpio0 18 GPIO_ACTIVE_LOW>;
5462306a36Sopenharmony_ci		};
5562306a36Sopenharmony_ci	};
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ci	soc {
5862306a36Sopenharmony_ci		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
5962306a36Sopenharmony_ci			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
6062306a36Sopenharmony_ci			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
6162306a36Sopenharmony_ci			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
6262306a36Sopenharmony_ci			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
6362306a36Sopenharmony_ci			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci		devbus-bootcs {
6662306a36Sopenharmony_ci			status = "okay";
6762306a36Sopenharmony_ci
6862306a36Sopenharmony_ci			/* Device Bus parameters are required */
6962306a36Sopenharmony_ci
7062306a36Sopenharmony_ci			/* Read parameters */
7162306a36Sopenharmony_ci			devbus,bus-width    = <16>;
7262306a36Sopenharmony_ci			devbus,turn-off-ps  = <60000>;
7362306a36Sopenharmony_ci			devbus,badr-skew-ps = <0>;
7462306a36Sopenharmony_ci			devbus,acc-first-ps = <124000>;
7562306a36Sopenharmony_ci			devbus,acc-next-ps  = <248000>;
7662306a36Sopenharmony_ci			devbus,rd-setup-ps  = <0>;
7762306a36Sopenharmony_ci			devbus,rd-hold-ps   = <0>;
7862306a36Sopenharmony_ci
7962306a36Sopenharmony_ci			/* Write parameters */
8062306a36Sopenharmony_ci			devbus,sync-enable = <0>;
8162306a36Sopenharmony_ci			devbus,wr-high-ps  = <60000>;
8262306a36Sopenharmony_ci			devbus,wr-low-ps   = <60000>;
8362306a36Sopenharmony_ci			devbus,ale-wr-ps   = <60000>;
8462306a36Sopenharmony_ci
8562306a36Sopenharmony_ci			/* NOR 16 MiB */
8662306a36Sopenharmony_ci			nor@0 {
8762306a36Sopenharmony_ci				compatible = "cfi-flash";
8862306a36Sopenharmony_ci				reg = <0 0x1000000>;
8962306a36Sopenharmony_ci				bank-width = <2>;
9062306a36Sopenharmony_ci			};
9162306a36Sopenharmony_ci		};
9262306a36Sopenharmony_ci
9362306a36Sopenharmony_ci		internal-regs {
9462306a36Sopenharmony_ci			serial@12000 {
9562306a36Sopenharmony_ci				status = "okay";
9662306a36Sopenharmony_ci			};
9762306a36Sopenharmony_ci			serial@12100 {
9862306a36Sopenharmony_ci				status = "okay";
9962306a36Sopenharmony_ci			};
10062306a36Sopenharmony_ci			serial@12200 {
10162306a36Sopenharmony_ci				status = "okay";
10262306a36Sopenharmony_ci			};
10362306a36Sopenharmony_ci			serial@12300 {
10462306a36Sopenharmony_ci				status = "okay";
10562306a36Sopenharmony_ci			};
10662306a36Sopenharmony_ci			pinctrl {
10762306a36Sopenharmony_ci				pinctrl-0 = <&pic_pins>;
10862306a36Sopenharmony_ci				pinctrl-names = "default";
10962306a36Sopenharmony_ci				pic_pins: pic-pins-0 {
11062306a36Sopenharmony_ci					marvell,pins = "mpp16", "mpp17",
11162306a36Sopenharmony_ci						       "mpp18";
11262306a36Sopenharmony_ci					marvell,function = "gpio";
11362306a36Sopenharmony_ci				};
11462306a36Sopenharmony_ci			};
11562306a36Sopenharmony_ci			sata@a0000 {
11662306a36Sopenharmony_ci				nr-ports = <2>;
11762306a36Sopenharmony_ci				status = "okay";
11862306a36Sopenharmony_ci			};
11962306a36Sopenharmony_ci
12062306a36Sopenharmony_ci			ethernet@70000 {
12162306a36Sopenharmony_ci				status = "okay";
12262306a36Sopenharmony_ci				phy = <&phy0>;
12362306a36Sopenharmony_ci				phy-mode = "qsgmii";
12462306a36Sopenharmony_ci				buffer-manager = <&bm>;
12562306a36Sopenharmony_ci				bm,pool-long = <0>;
12662306a36Sopenharmony_ci			};
12762306a36Sopenharmony_ci			ethernet@74000 {
12862306a36Sopenharmony_ci				status = "okay";
12962306a36Sopenharmony_ci				phy = <&phy1>;
13062306a36Sopenharmony_ci				phy-mode = "qsgmii";
13162306a36Sopenharmony_ci				buffer-manager = <&bm>;
13262306a36Sopenharmony_ci				bm,pool-long = <1>;
13362306a36Sopenharmony_ci			};
13462306a36Sopenharmony_ci			ethernet@30000 {
13562306a36Sopenharmony_ci				status = "okay";
13662306a36Sopenharmony_ci				phy = <&phy2>;
13762306a36Sopenharmony_ci				phy-mode = "qsgmii";
13862306a36Sopenharmony_ci				buffer-manager = <&bm>;
13962306a36Sopenharmony_ci				bm,pool-long = <2>;
14062306a36Sopenharmony_ci			};
14162306a36Sopenharmony_ci			ethernet@34000 {
14262306a36Sopenharmony_ci				status = "okay";
14362306a36Sopenharmony_ci				phy = <&phy3>;
14462306a36Sopenharmony_ci				phy-mode = "qsgmii";
14562306a36Sopenharmony_ci				buffer-manager = <&bm>;
14662306a36Sopenharmony_ci				bm,pool-long = <3>;
14762306a36Sopenharmony_ci			};
14862306a36Sopenharmony_ci
14962306a36Sopenharmony_ci			/* Front-side USB slot */
15062306a36Sopenharmony_ci			usb@50000 {
15162306a36Sopenharmony_ci				status = "okay";
15262306a36Sopenharmony_ci			};
15362306a36Sopenharmony_ci
15462306a36Sopenharmony_ci			/* Back-side USB slot */
15562306a36Sopenharmony_ci			usb@51000 {
15662306a36Sopenharmony_ci				status = "okay";
15762306a36Sopenharmony_ci			};
15862306a36Sopenharmony_ci
15962306a36Sopenharmony_ci			bm@c0000 {
16062306a36Sopenharmony_ci				status = "okay";
16162306a36Sopenharmony_ci			};
16262306a36Sopenharmony_ci
16362306a36Sopenharmony_ci			nand-controller@d0000 {
16462306a36Sopenharmony_ci				status = "okay";
16562306a36Sopenharmony_ci
16662306a36Sopenharmony_ci				nand@0 {
16762306a36Sopenharmony_ci					reg = <0>;
16862306a36Sopenharmony_ci					label = "pxa3xx_nand-0";
16962306a36Sopenharmony_ci					nand-rb = <0>;
17062306a36Sopenharmony_ci					nand-on-flash-bbt;
17162306a36Sopenharmony_ci				};
17262306a36Sopenharmony_ci			};
17362306a36Sopenharmony_ci		};
17462306a36Sopenharmony_ci
17562306a36Sopenharmony_ci		bm-bppi {
17662306a36Sopenharmony_ci			status = "okay";
17762306a36Sopenharmony_ci		};
17862306a36Sopenharmony_ci	};
17962306a36Sopenharmony_ci};
18062306a36Sopenharmony_ci
18162306a36Sopenharmony_ci&pciec {
18262306a36Sopenharmony_ci	status = "okay";
18362306a36Sopenharmony_ci
18462306a36Sopenharmony_ci	/*
18562306a36Sopenharmony_ci	 * The 3 slots are physically present as
18662306a36Sopenharmony_ci	 * standard PCIe slots on the board.
18762306a36Sopenharmony_ci	 */
18862306a36Sopenharmony_ci	pcie@1,0 {
18962306a36Sopenharmony_ci		/* Port 0, Lane 0 */
19062306a36Sopenharmony_ci		status = "okay";
19162306a36Sopenharmony_ci	};
19262306a36Sopenharmony_ci	pcie@9,0 {
19362306a36Sopenharmony_ci		/* Port 2, Lane 0 */
19462306a36Sopenharmony_ci		status = "okay";
19562306a36Sopenharmony_ci	};
19662306a36Sopenharmony_ci	pcie@a,0 {
19762306a36Sopenharmony_ci		/* Port 3, Lane 0 */
19862306a36Sopenharmony_ci		status = "okay";
19962306a36Sopenharmony_ci	};
20062306a36Sopenharmony_ci};
20162306a36Sopenharmony_ci
20262306a36Sopenharmony_ci&mdio {
20362306a36Sopenharmony_ci	phy0: ethernet-phy@0 {
20462306a36Sopenharmony_ci		reg = <16>;
20562306a36Sopenharmony_ci	};
20662306a36Sopenharmony_ci
20762306a36Sopenharmony_ci	phy1: ethernet-phy@1 {
20862306a36Sopenharmony_ci		reg = <17>;
20962306a36Sopenharmony_ci	};
21062306a36Sopenharmony_ci
21162306a36Sopenharmony_ci	phy2: ethernet-phy@2 {
21262306a36Sopenharmony_ci		reg = <18>;
21362306a36Sopenharmony_ci	};
21462306a36Sopenharmony_ci
21562306a36Sopenharmony_ci	phy3: ethernet-phy@3 {
21662306a36Sopenharmony_ci		reg = <19>;
21762306a36Sopenharmony_ci	};
21862306a36Sopenharmony_ci};
21962306a36Sopenharmony_ci
22062306a36Sopenharmony_ci&spi0 {
22162306a36Sopenharmony_ci	status = "okay";
22262306a36Sopenharmony_ci
22362306a36Sopenharmony_ci	flash@0 {
22462306a36Sopenharmony_ci		#address-cells = <1>;
22562306a36Sopenharmony_ci		#size-cells = <1>;
22662306a36Sopenharmony_ci		compatible = "n25q128a13", "jedec,spi-nor";
22762306a36Sopenharmony_ci		reg = <0>; /* Chip select 0 */
22862306a36Sopenharmony_ci		spi-max-frequency = <108000000>;
22962306a36Sopenharmony_ci	};
23062306a36Sopenharmony_ci};
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