162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Device Tree Include file for Marvell Armada 385 SoC. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2014 Marvell 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Lior Amsalem <alior@marvell.com> 862306a36Sopenharmony_ci * Gregory CLEMENT <gregory.clement@free-electrons.com> 962306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 1062306a36Sopenharmony_ci */ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci#include "armada-38x.dtsi" 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/ { 1562306a36Sopenharmony_ci model = "Marvell Armada 385 family SoC"; 1662306a36Sopenharmony_ci compatible = "marvell,armada385", "marvell,armada380"; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci cpus { 1962306a36Sopenharmony_ci #address-cells = <1>; 2062306a36Sopenharmony_ci #size-cells = <0>; 2162306a36Sopenharmony_ci enable-method = "marvell,armada-380-smp"; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci cpu@0 { 2462306a36Sopenharmony_ci device_type = "cpu"; 2562306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 2662306a36Sopenharmony_ci reg = <0>; 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci cpu@1 { 2962306a36Sopenharmony_ci device_type = "cpu"; 3062306a36Sopenharmony_ci compatible = "arm,cortex-a9"; 3162306a36Sopenharmony_ci reg = <1>; 3262306a36Sopenharmony_ci }; 3362306a36Sopenharmony_ci }; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci soc { 3662306a36Sopenharmony_ci pciec: pcie { 3762306a36Sopenharmony_ci compatible = "marvell,armada-370-pcie"; 3862306a36Sopenharmony_ci status = "disabled"; 3962306a36Sopenharmony_ci device_type = "pci"; 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci #address-cells = <3>; 4262306a36Sopenharmony_ci #size-cells = <2>; 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci msi-parent = <&mpic>; 4562306a36Sopenharmony_ci bus-range = <0x00 0xff>; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci ranges = 4862306a36Sopenharmony_ci <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 4962306a36Sopenharmony_ci 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 5062306a36Sopenharmony_ci 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 5162306a36Sopenharmony_ci 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 5262306a36Sopenharmony_ci 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 5362306a36Sopenharmony_ci 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 5462306a36Sopenharmony_ci 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 5562306a36Sopenharmony_ci 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 5662306a36Sopenharmony_ci 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 5762306a36Sopenharmony_ci 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 5862306a36Sopenharmony_ci 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 5962306a36Sopenharmony_ci 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci /* 6262306a36Sopenharmony_ci * This port can be either x4 or x1. When 6362306a36Sopenharmony_ci * configured in x4 by the bootloader, then 6462306a36Sopenharmony_ci * pcie@4,0 is not available. 6562306a36Sopenharmony_ci */ 6662306a36Sopenharmony_ci pcie1: pcie@1,0 { 6762306a36Sopenharmony_ci device_type = "pci"; 6862306a36Sopenharmony_ci assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 6962306a36Sopenharmony_ci reg = <0x0800 0 0 0 0>; 7062306a36Sopenharmony_ci #address-cells = <3>; 7162306a36Sopenharmony_ci #size-cells = <2>; 7262306a36Sopenharmony_ci interrupt-names = "intx"; 7362306a36Sopenharmony_ci interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 7462306a36Sopenharmony_ci #interrupt-cells = <1>; 7562306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 7662306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x1 0 1 0>; 7762306a36Sopenharmony_ci bus-range = <0x00 0xff>; 7862306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 7962306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie1_intc 0>, 8062306a36Sopenharmony_ci <0 0 0 2 &pcie1_intc 1>, 8162306a36Sopenharmony_ci <0 0 0 3 &pcie1_intc 2>, 8262306a36Sopenharmony_ci <0 0 0 4 &pcie1_intc 3>; 8362306a36Sopenharmony_ci marvell,pcie-port = <0>; 8462306a36Sopenharmony_ci marvell,pcie-lane = <0>; 8562306a36Sopenharmony_ci clocks = <&gateclk 8>; 8662306a36Sopenharmony_ci status = "disabled"; 8762306a36Sopenharmony_ci pcie1_intc: interrupt-controller { 8862306a36Sopenharmony_ci interrupt-controller; 8962306a36Sopenharmony_ci #interrupt-cells = <1>; 9062306a36Sopenharmony_ci }; 9162306a36Sopenharmony_ci }; 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci /* x1 port */ 9462306a36Sopenharmony_ci pcie2: pcie@2,0 { 9562306a36Sopenharmony_ci device_type = "pci"; 9662306a36Sopenharmony_ci assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; 9762306a36Sopenharmony_ci reg = <0x1000 0 0 0 0>; 9862306a36Sopenharmony_ci #address-cells = <3>; 9962306a36Sopenharmony_ci #size-cells = <2>; 10062306a36Sopenharmony_ci interrupt-names = "intx"; 10162306a36Sopenharmony_ci interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 10262306a36Sopenharmony_ci #interrupt-cells = <1>; 10362306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 10462306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x2 0 1 0>; 10562306a36Sopenharmony_ci bus-range = <0x00 0xff>; 10662306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 10762306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie2_intc 0>, 10862306a36Sopenharmony_ci <0 0 0 2 &pcie2_intc 1>, 10962306a36Sopenharmony_ci <0 0 0 3 &pcie2_intc 2>, 11062306a36Sopenharmony_ci <0 0 0 4 &pcie2_intc 3>; 11162306a36Sopenharmony_ci marvell,pcie-port = <1>; 11262306a36Sopenharmony_ci marvell,pcie-lane = <0>; 11362306a36Sopenharmony_ci clocks = <&gateclk 5>; 11462306a36Sopenharmony_ci status = "disabled"; 11562306a36Sopenharmony_ci pcie2_intc: interrupt-controller { 11662306a36Sopenharmony_ci interrupt-controller; 11762306a36Sopenharmony_ci #interrupt-cells = <1>; 11862306a36Sopenharmony_ci }; 11962306a36Sopenharmony_ci }; 12062306a36Sopenharmony_ci 12162306a36Sopenharmony_ci /* x1 port */ 12262306a36Sopenharmony_ci pcie3: pcie@3,0 { 12362306a36Sopenharmony_ci device_type = "pci"; 12462306a36Sopenharmony_ci assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; 12562306a36Sopenharmony_ci reg = <0x1800 0 0 0 0>; 12662306a36Sopenharmony_ci #address-cells = <3>; 12762306a36Sopenharmony_ci #size-cells = <2>; 12862306a36Sopenharmony_ci interrupt-names = "intx"; 12962306a36Sopenharmony_ci interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 13062306a36Sopenharmony_ci #interrupt-cells = <1>; 13162306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 13262306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x3 0 1 0>; 13362306a36Sopenharmony_ci bus-range = <0x00 0xff>; 13462306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 13562306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie3_intc 0>, 13662306a36Sopenharmony_ci <0 0 0 2 &pcie3_intc 1>, 13762306a36Sopenharmony_ci <0 0 0 3 &pcie3_intc 2>, 13862306a36Sopenharmony_ci <0 0 0 4 &pcie3_intc 3>; 13962306a36Sopenharmony_ci marvell,pcie-port = <2>; 14062306a36Sopenharmony_ci marvell,pcie-lane = <0>; 14162306a36Sopenharmony_ci clocks = <&gateclk 6>; 14262306a36Sopenharmony_ci status = "disabled"; 14362306a36Sopenharmony_ci pcie3_intc: interrupt-controller { 14462306a36Sopenharmony_ci interrupt-controller; 14562306a36Sopenharmony_ci #interrupt-cells = <1>; 14662306a36Sopenharmony_ci }; 14762306a36Sopenharmony_ci }; 14862306a36Sopenharmony_ci 14962306a36Sopenharmony_ci /* 15062306a36Sopenharmony_ci * x1 port only available when pcie@1,0 is 15162306a36Sopenharmony_ci * configured as a x1 port 15262306a36Sopenharmony_ci */ 15362306a36Sopenharmony_ci pcie4: pcie@4,0 { 15462306a36Sopenharmony_ci device_type = "pci"; 15562306a36Sopenharmony_ci assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; 15662306a36Sopenharmony_ci reg = <0x2000 0 0 0 0>; 15762306a36Sopenharmony_ci #address-cells = <3>; 15862306a36Sopenharmony_ci #size-cells = <2>; 15962306a36Sopenharmony_ci interrupt-names = "intx"; 16062306a36Sopenharmony_ci interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 16162306a36Sopenharmony_ci #interrupt-cells = <1>; 16262306a36Sopenharmony_ci ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 16362306a36Sopenharmony_ci 0x81000000 0 0 0x81000000 0x4 0 1 0>; 16462306a36Sopenharmony_ci bus-range = <0x00 0xff>; 16562306a36Sopenharmony_ci interrupt-map-mask = <0 0 0 7>; 16662306a36Sopenharmony_ci interrupt-map = <0 0 0 1 &pcie4_intc 0>, 16762306a36Sopenharmony_ci <0 0 0 2 &pcie4_intc 1>, 16862306a36Sopenharmony_ci <0 0 0 3 &pcie4_intc 2>, 16962306a36Sopenharmony_ci <0 0 0 4 &pcie4_intc 3>; 17062306a36Sopenharmony_ci marvell,pcie-port = <3>; 17162306a36Sopenharmony_ci marvell,pcie-lane = <0>; 17262306a36Sopenharmony_ci clocks = <&gateclk 7>; 17362306a36Sopenharmony_ci status = "disabled"; 17462306a36Sopenharmony_ci pcie4_intc: interrupt-controller { 17562306a36Sopenharmony_ci interrupt-controller; 17662306a36Sopenharmony_ci #interrupt-cells = <1>; 17762306a36Sopenharmony_ci }; 17862306a36Sopenharmony_ci }; 17962306a36Sopenharmony_ci }; 18062306a36Sopenharmony_ci }; 18162306a36Sopenharmony_ci}; 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ci&pinctrl { 18462306a36Sopenharmony_ci compatible = "marvell,mv88f6820-pinctrl"; 18562306a36Sopenharmony_ci}; 186