162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree file for Marvell Armada 375 evaluation board
462306a36Sopenharmony_ci * (DB-88F6720)
562306a36Sopenharmony_ci *
662306a36Sopenharmony_ci *  Copyright (C) 2014 Marvell
762306a36Sopenharmony_ci *
862306a36Sopenharmony_ci * Gregory CLEMENT <gregory.clement@free-electrons.com>
962306a36Sopenharmony_ci * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
1062306a36Sopenharmony_ci */
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci/dts-v1/;
1362306a36Sopenharmony_ci#include <dt-bindings/gpio/gpio.h>
1462306a36Sopenharmony_ci#include "armada-375.dtsi"
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci/ {
1762306a36Sopenharmony_ci	model = "Marvell Armada 375 Development Board";
1862306a36Sopenharmony_ci	compatible = "marvell,a375-db", "marvell,armada375";
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci	chosen {
2162306a36Sopenharmony_ci		stdout-path = "serial0:115200n8";
2262306a36Sopenharmony_ci	};
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci	memory@0 {
2562306a36Sopenharmony_ci		device_type = "memory";
2662306a36Sopenharmony_ci		reg = <0x00000000 0x40000000>; /* 1 GB */
2762306a36Sopenharmony_ci	};
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci	soc {
3062306a36Sopenharmony_ci		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
3162306a36Sopenharmony_ci			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
3262306a36Sopenharmony_ci			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
3362306a36Sopenharmony_ci			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci	};
3662306a36Sopenharmony_ci};
3762306a36Sopenharmony_ci&pciec {
3862306a36Sopenharmony_ci	status = "okay";
3962306a36Sopenharmony_ci};
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci/*
4262306a36Sopenharmony_ci * The two PCIe units are accessible through
4362306a36Sopenharmony_ci * standard PCIe slots on the board.
4462306a36Sopenharmony_ci */
4562306a36Sopenharmony_ci&pcie0 {
4662306a36Sopenharmony_ci	/* Port 0, Lane 0 */
4762306a36Sopenharmony_ci	status = "okay";
4862306a36Sopenharmony_ci};
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci&pcie1 {
5162306a36Sopenharmony_ci	/* Port 1, Lane 0 */
5262306a36Sopenharmony_ci	status = "okay";
5362306a36Sopenharmony_ci};
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci&spi0 {
5762306a36Sopenharmony_ci	pinctrl-0 = <&spi0_pins>;
5862306a36Sopenharmony_ci	pinctrl-names = "default";
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci	/*
6162306a36Sopenharmony_ci	 * SPI conflicts with NAND, so we disable it here, and
6262306a36Sopenharmony_ci	 * select NAND as the enabled device by default.
6362306a36Sopenharmony_ci	 */
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci	status = "disabled";
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci	flash@0 {
6862306a36Sopenharmony_ci		#address-cells = <1>;
6962306a36Sopenharmony_ci		#size-cells = <1>;
7062306a36Sopenharmony_ci		compatible = "n25q128a13", "jedec,spi-nor";
7162306a36Sopenharmony_ci		reg = <0>; /* Chip select 0 */
7262306a36Sopenharmony_ci		spi-max-frequency = <108000000>;
7362306a36Sopenharmony_ci	};
7462306a36Sopenharmony_ci};
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_ci&i2c0 {
7762306a36Sopenharmony_ci	status = "okay";
7862306a36Sopenharmony_ci	clock-frequency = <100000>;
7962306a36Sopenharmony_ci	pinctrl-0 = <&i2c0_pins>;
8062306a36Sopenharmony_ci	pinctrl-names = "default";
8162306a36Sopenharmony_ci};
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci&i2c1 {
8462306a36Sopenharmony_ci	status = "okay";
8562306a36Sopenharmony_ci	clock-frequency = <100000>;
8662306a36Sopenharmony_ci	pinctrl-0 = <&i2c1_pins>;
8762306a36Sopenharmony_ci	pinctrl-names = "default";
8862306a36Sopenharmony_ci};
8962306a36Sopenharmony_ci
9062306a36Sopenharmony_ci&uart0 {
9162306a36Sopenharmony_ci	status = "okay";
9262306a36Sopenharmony_ci};
9362306a36Sopenharmony_ci
9462306a36Sopenharmony_ci&pinctrl {
9562306a36Sopenharmony_ci	sdio_st_pins: sdio-st-pins {
9662306a36Sopenharmony_ci		marvell,pins = "mpp44", "mpp45";
9762306a36Sopenharmony_ci		marvell,function = "gpio";
9862306a36Sopenharmony_ci	};
9962306a36Sopenharmony_ci};
10062306a36Sopenharmony_ci
10162306a36Sopenharmony_ci&sata {
10262306a36Sopenharmony_ci	status = "okay";
10362306a36Sopenharmony_ci	nr-ports = <2>;
10462306a36Sopenharmony_ci};
10562306a36Sopenharmony_ci
10662306a36Sopenharmony_ci&nand_controller {
10762306a36Sopenharmony_ci	status = "okay";
10862306a36Sopenharmony_ci	pinctrl-0 = <&nand_pins>;
10962306a36Sopenharmony_ci	pinctrl-names = "default";
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ci	nand@0 {
11262306a36Sopenharmony_ci		reg = <0>;
11362306a36Sopenharmony_ci		label = "pxa3xx_nand-0";
11462306a36Sopenharmony_ci		nand-rb = <0>;
11562306a36Sopenharmony_ci		marvell,nand-keep-config;
11662306a36Sopenharmony_ci		nand-on-flash-bbt;
11762306a36Sopenharmony_ci		nand-ecc-strength = <4>;
11862306a36Sopenharmony_ci		nand-ecc-step-size = <512>;
11962306a36Sopenharmony_ci
12062306a36Sopenharmony_ci		partitions {
12162306a36Sopenharmony_ci			compatible = "fixed-partitions";
12262306a36Sopenharmony_ci			#address-cells = <1>;
12362306a36Sopenharmony_ci			#size-cells = <1>;
12462306a36Sopenharmony_ci
12562306a36Sopenharmony_ci			partition@0 {
12662306a36Sopenharmony_ci				label = "U-Boot";
12762306a36Sopenharmony_ci				reg = <0 0x800000>;
12862306a36Sopenharmony_ci			};
12962306a36Sopenharmony_ci			partition@800000 {
13062306a36Sopenharmony_ci				label = "Linux";
13162306a36Sopenharmony_ci				reg = <0x800000 0x800000>;
13262306a36Sopenharmony_ci			};
13362306a36Sopenharmony_ci			partition@1000000 {
13462306a36Sopenharmony_ci				label = "Filesystem";
13562306a36Sopenharmony_ci				reg = <0x1000000 0x3f000000>;
13662306a36Sopenharmony_ci			};
13762306a36Sopenharmony_ci		};
13862306a36Sopenharmony_ci	};
13962306a36Sopenharmony_ci};
14062306a36Sopenharmony_ci
14162306a36Sopenharmony_ci&usb1 {
14262306a36Sopenharmony_ci	status = "okay";
14362306a36Sopenharmony_ci};
14462306a36Sopenharmony_ci
14562306a36Sopenharmony_ci&usb2 {
14662306a36Sopenharmony_ci	status = "okay";
14762306a36Sopenharmony_ci};
14862306a36Sopenharmony_ci
14962306a36Sopenharmony_ci&sdio {
15062306a36Sopenharmony_ci	pinctrl-0 = <&sdio_pins &sdio_st_pins>;
15162306a36Sopenharmony_ci	pinctrl-names = "default";
15262306a36Sopenharmony_ci	status = "okay";
15362306a36Sopenharmony_ci	cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
15462306a36Sopenharmony_ci	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
15562306a36Sopenharmony_ci};
15662306a36Sopenharmony_ci
15762306a36Sopenharmony_ci&mdio {
15862306a36Sopenharmony_ci	phy0: ethernet-phy@0 {
15962306a36Sopenharmony_ci		reg = <0>;
16062306a36Sopenharmony_ci	};
16162306a36Sopenharmony_ci
16262306a36Sopenharmony_ci	phy3: ethernet-phy@3 {
16362306a36Sopenharmony_ci		reg = <3>;
16462306a36Sopenharmony_ci	};
16562306a36Sopenharmony_ci};
16662306a36Sopenharmony_ci
16762306a36Sopenharmony_ci&ethernet {
16862306a36Sopenharmony_ci	status = "okay";
16962306a36Sopenharmony_ci};
17062306a36Sopenharmony_ci
17162306a36Sopenharmony_ci
17262306a36Sopenharmony_ci&eth0 {
17362306a36Sopenharmony_ci	status = "okay";
17462306a36Sopenharmony_ci	phy = <&phy0>;
17562306a36Sopenharmony_ci	phy-mode = "rgmii-id";
17662306a36Sopenharmony_ci};
17762306a36Sopenharmony_ci
17862306a36Sopenharmony_ci&eth1 {
17962306a36Sopenharmony_ci	status = "okay";
18062306a36Sopenharmony_ci	phy = <&phy3>;
18162306a36Sopenharmony_ci	phy-mode = "gmii";
18262306a36Sopenharmony_ci};
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