1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 *
5 *  vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
6 *   -flush_cache_dup_mm (fork)
7 *   -likewise for flush_cache_mm (exit/execve)
8 *   -likewise for flush_cache_{range,page} (munmap, exit, COW-break)
9 *
10 *  vineetg: April 2008
11 *   -Added a critical CacheLine flush to copy_to_user_page( ) which
12 *     was causing gdbserver to not setup breakpoints consistently
13 */
14
15#ifndef _ASM_CACHEFLUSH_H
16#define _ASM_CACHEFLUSH_H
17
18#include <linux/mm.h>
19#include <asm/shmparam.h>
20
21void flush_cache_all(void);
22
23void flush_icache_range(unsigned long kstart, unsigned long kend);
24void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
25void __inv_icache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
26void __flush_dcache_pages(phys_addr_t paddr, unsigned long vaddr, unsigned nr);
27
28#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
29
30void flush_dcache_page(struct page *page);
31void flush_dcache_folio(struct folio *folio);
32#define flush_dcache_folio flush_dcache_folio
33
34void dma_cache_wback_inv(phys_addr_t start, unsigned long sz);
35void dma_cache_inv(phys_addr_t start, unsigned long sz);
36void dma_cache_wback(phys_addr_t start, unsigned long sz);
37
38#define flush_dcache_mmap_lock(mapping)		do { } while (0)
39#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
40
41/* TBD: optimize this */
42#define flush_cache_vmap(start, end)		flush_cache_all()
43#define flush_cache_vmap_early(start, end)	do { } while (0)
44#define flush_cache_vunmap(start, end)		flush_cache_all()
45
46#define flush_cache_dup_mm(mm)			/* called on fork (VIVT only) */
47
48#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
49
50#define flush_cache_mm(mm)			/* called on munmap/exit */
51#define flush_cache_range(mm, u_vstart, u_vend)
52#define flush_cache_page(vma, u_vaddr, pfn)	/* PF handling/COW-break */
53
54#else	/* VIPT aliasing dcache */
55
56/* To clear out stale userspace mappings */
57void flush_cache_mm(struct mm_struct *mm);
58void flush_cache_range(struct vm_area_struct *vma,
59	unsigned long start,unsigned long end);
60void flush_cache_page(struct vm_area_struct *vma,
61	unsigned long user_addr, unsigned long page);
62
63/*
64 * To make sure that userspace mapping is flushed to memory before
65 * get_user_pages() uses a kernel mapping to access the page
66 */
67#define ARCH_HAS_FLUSH_ANON_PAGE
68void flush_anon_page(struct vm_area_struct *vma,
69	struct page *page, unsigned long u_vaddr);
70
71#endif	/* CONFIG_ARC_CACHE_VIPT_ALIASING */
72
73/*
74 * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
75 * This works around some PIO based drivers which don't call flush_dcache_page
76 * to record that they dirtied the dcache
77 */
78#define PG_dc_clean	PG_arch_1
79
80#define CACHE_COLORS_NUM	4
81#define CACHE_COLORS_MSK	(CACHE_COLORS_NUM - 1)
82#define CACHE_COLOR(addr)	(((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)
83
84/*
85 * Simple wrapper over config option
86 * Bootup code ensures that hardware matches kernel configuration
87 */
88static inline int cache_is_vipt_aliasing(void)
89{
90	return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
91}
92
93/*
94 * checks if two addresses (after page aligning) index into same cache set
95 */
96#define addr_not_cache_congruent(addr1, addr2)				\
97({									\
98	cache_is_vipt_aliasing() ? 					\
99		(CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0;		\
100})
101
102#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
103do {									\
104	memcpy(dst, src, len);						\
105	if (vma->vm_flags & VM_EXEC)					\
106		__sync_icache_dcache((unsigned long)(dst), vaddr, len);	\
107} while (0)
108
109#define copy_from_user_page(vma, page, vaddr, dst, src, len)		\
110	memcpy(dst, src, len);						\
111
112#endif
113