162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci/* 762306a36Sopenharmony_ci * Device tree for AXC001 770D/EM6/AS221 CPU card 862306a36Sopenharmony_ci * Note that this file only supports the 770D CPU 962306a36Sopenharmony_ci */ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/include/ "skeleton.dtsi" 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/ { 1462306a36Sopenharmony_ci compatible = "snps,arc"; 1562306a36Sopenharmony_ci #address-cells = <2>; 1662306a36Sopenharmony_ci #size-cells = <2>; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci cpu_card { 1962306a36Sopenharmony_ci compatible = "simple-bus"; 2062306a36Sopenharmony_ci #address-cells = <1>; 2162306a36Sopenharmony_ci #size-cells = <1>; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci core_clk: core_clk { 2662306a36Sopenharmony_ci #clock-cells = <0>; 2762306a36Sopenharmony_ci compatible = "fixed-clock"; 2862306a36Sopenharmony_ci clock-frequency = <750000000>; 2962306a36Sopenharmony_ci }; 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci input_clk: input-clk { 3262306a36Sopenharmony_ci #clock-cells = <0>; 3362306a36Sopenharmony_ci compatible = "fixed-clock"; 3462306a36Sopenharmony_ci clock-frequency = <33333333>; 3562306a36Sopenharmony_ci }; 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci core_intc: arc700-intc@cpu { 3862306a36Sopenharmony_ci compatible = "snps,arc700-intc"; 3962306a36Sopenharmony_ci interrupt-controller; 4062306a36Sopenharmony_ci #interrupt-cells = <1>; 4162306a36Sopenharmony_ci }; 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci /* 4462306a36Sopenharmony_ci * this GPIO block ORs all interrupts on CPU card (creg,..) 4562306a36Sopenharmony_ci * to uplink only 1 IRQ to ARC core intc 4662306a36Sopenharmony_ci */ 4762306a36Sopenharmony_ci dw-apb-gpio@2000 { 4862306a36Sopenharmony_ci compatible = "snps,dw-apb-gpio"; 4962306a36Sopenharmony_ci reg = < 0x2000 0x80 >; 5062306a36Sopenharmony_ci #address-cells = <1>; 5162306a36Sopenharmony_ci #size-cells = <0>; 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ci ictl_intc: gpio-controller@0 { 5462306a36Sopenharmony_ci compatible = "snps,dw-apb-gpio-port"; 5562306a36Sopenharmony_ci gpio-controller; 5662306a36Sopenharmony_ci #gpio-cells = <2>; 5762306a36Sopenharmony_ci snps,nr-gpios = <30>; 5862306a36Sopenharmony_ci reg = <0>; 5962306a36Sopenharmony_ci interrupt-controller; 6062306a36Sopenharmony_ci #interrupt-cells = <2>; 6162306a36Sopenharmony_ci interrupt-parent = <&core_intc>; 6262306a36Sopenharmony_ci interrupts = <15>; 6362306a36Sopenharmony_ci }; 6462306a36Sopenharmony_ci }; 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci debug_uart: dw-apb-uart@5000 { 6762306a36Sopenharmony_ci compatible = "snps,dw-apb-uart"; 6862306a36Sopenharmony_ci reg = <0x5000 0x100>; 6962306a36Sopenharmony_ci clock-frequency = <33333000>; 7062306a36Sopenharmony_ci interrupt-parent = <&ictl_intc>; 7162306a36Sopenharmony_ci interrupts = <19 4>; 7262306a36Sopenharmony_ci baud = <115200>; 7362306a36Sopenharmony_ci reg-shift = <2>; 7462306a36Sopenharmony_ci reg-io-width = <4>; 7562306a36Sopenharmony_ci }; 7662306a36Sopenharmony_ci 7762306a36Sopenharmony_ci arcpct0: pct { 7862306a36Sopenharmony_ci compatible = "snps,arc700-pct"; 7962306a36Sopenharmony_ci }; 8062306a36Sopenharmony_ci }; 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci /* 8362306a36Sopenharmony_ci * This INTC is actually connected to DW APB GPIO 8462306a36Sopenharmony_ci * which acts as a wire between MB INTC and CPU INTC. 8562306a36Sopenharmony_ci * GPIO INTC is configured in platform init code 8662306a36Sopenharmony_ci * and here we mimic direct connection from MB INTC to 8762306a36Sopenharmony_ci * CPU INTC, thus we set "interrupts = <7>" instead of 8862306a36Sopenharmony_ci * "interrupts = <12>" 8962306a36Sopenharmony_ci * 9062306a36Sopenharmony_ci * This intc actually resides on MB, but we move it here to 9162306a36Sopenharmony_ci * avoid duplicating the MB dtsi file given that IRQ from 9262306a36Sopenharmony_ci * this intc to cpu intc are different for axs101 and axs103 9362306a36Sopenharmony_ci */ 9462306a36Sopenharmony_ci mb_intc: interrupt-controller@e0012000 { 9562306a36Sopenharmony_ci #interrupt-cells = <1>; 9662306a36Sopenharmony_ci compatible = "snps,dw-apb-ictl"; 9762306a36Sopenharmony_ci reg = < 0x0 0xe0012000 0x0 0x200 >; 9862306a36Sopenharmony_ci interrupt-controller; 9962306a36Sopenharmony_ci interrupt-parent = <&core_intc>; 10062306a36Sopenharmony_ci interrupts = < 7 >; 10162306a36Sopenharmony_ci }; 10262306a36Sopenharmony_ci 10362306a36Sopenharmony_ci memory { 10462306a36Sopenharmony_ci device_type = "memory"; 10562306a36Sopenharmony_ci /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ 10662306a36Sopenharmony_ci reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ 10762306a36Sopenharmony_ci }; 10862306a36Sopenharmony_ci 10962306a36Sopenharmony_ci reserved-memory { 11062306a36Sopenharmony_ci #address-cells = <2>; 11162306a36Sopenharmony_ci #size-cells = <2>; 11262306a36Sopenharmony_ci ranges; 11362306a36Sopenharmony_ci /* 11462306a36Sopenharmony_ci * We just move frame buffer area to the very end of 11562306a36Sopenharmony_ci * available DDR. And even though in case of ARC770 there's 11662306a36Sopenharmony_ci * no strict requirement for a frame-buffer to be in any 11762306a36Sopenharmony_ci * particular location it allows us to use the same 11862306a36Sopenharmony_ci * base board's DT node for ARC PGU as for ARc HS38. 11962306a36Sopenharmony_ci */ 12062306a36Sopenharmony_ci frame_buffer: frame_buffer@9e000000 { 12162306a36Sopenharmony_ci compatible = "shared-dma-pool"; 12262306a36Sopenharmony_ci reg = <0x0 0x9e000000 0x0 0x2000000>; 12362306a36Sopenharmony_ci no-map; 12462306a36Sopenharmony_ci }; 12562306a36Sopenharmony_ci }; 12662306a36Sopenharmony_ci}; 127