162306a36Sopenharmony_ci============================================= 262306a36Sopenharmony_ciBroadcom Starfighter 2 Ethernet switch driver 362306a36Sopenharmony_ci============================================= 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciBroadcom's Starfighter 2 Ethernet switch hardware block is commonly found and 662306a36Sopenharmony_cideployed in the following products: 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci- xDSL gateways such as BCM63138 962306a36Sopenharmony_ci- streaming/multimedia Set Top Box such as BCM7445 1062306a36Sopenharmony_ci- Cable Modem/residential gateways such as BCM7145/BCM3390 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciThe switch is typically deployed in a configuration involving between 5 to 13 1362306a36Sopenharmony_ciports, offering a range of built-in and customizable interfaces: 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci- single integrated Gigabit PHY 1662306a36Sopenharmony_ci- quad integrated Gigabit PHY 1762306a36Sopenharmony_ci- quad external Gigabit PHY w/ MDIO multiplexer 1862306a36Sopenharmony_ci- integrated MoCA PHY 1962306a36Sopenharmony_ci- several external MII/RevMII/GMII/RGMII interfaces 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ciThe switch also supports specific congestion control features which allow MoCA 2262306a36Sopenharmony_cifail-over not to lose packets during a MoCA role re-election, as well as out of 2362306a36Sopenharmony_ciband back-pressure to the host CPU network interface when downstream interfaces 2462306a36Sopenharmony_ciare connected at a lower speed. 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciThe switch hardware block is typically interfaced using MMIO accesses and 2762306a36Sopenharmony_cicontains a bunch of sub-blocks/registers: 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci- ``SWITCH_CORE``: common switch registers 3062306a36Sopenharmony_ci- ``SWITCH_REG``: external interfaces switch register 3162306a36Sopenharmony_ci- ``SWITCH_MDIO``: external MDIO bus controller (there is another one in SWITCH_CORE, 3262306a36Sopenharmony_ci which is used for indirect PHY accesses) 3362306a36Sopenharmony_ci- ``SWITCH_INDIR_RW``: 64-bits wide register helper block 3462306a36Sopenharmony_ci- ``SWITCH_INTRL2_0/1``: Level-2 interrupt controllers 3562306a36Sopenharmony_ci- ``SWITCH_ACB``: Admission control block 3662306a36Sopenharmony_ci- ``SWITCH_FCB``: Fail-over control block 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ciImplementation details 3962306a36Sopenharmony_ci====================== 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciThe driver is located in ``drivers/net/dsa/bcm_sf2.c`` and is implemented as a DSA 4262306a36Sopenharmony_cidriver; see ``Documentation/networking/dsa/dsa.rst`` for details on the subsystem 4362306a36Sopenharmony_ciand what it provides. 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ciThe SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag 4662306a36Sopenharmony_ciwhich gets inserted by the switch for every packet forwarded to the CPU 4762306a36Sopenharmony_ciinterface, conversely, the CPU network interface should insert a similar tag for 4862306a36Sopenharmony_cipackets entering the CPU port. The tag format is described in 4962306a36Sopenharmony_ci``net/dsa/tag_brcm.c``. 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ciOverall, the SF2 driver is a fairly regular DSA driver; there are a few 5262306a36Sopenharmony_cispecifics covered below. 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciDevice Tree probing 5562306a36Sopenharmony_ci------------------- 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciThe DSA platform device driver is probed using a specific compatible string 5862306a36Sopenharmony_ciprovided in ``net/dsa/dsa.c``. The reason for that is because the DSA subsystem gets 5962306a36Sopenharmony_ciregistered as a platform device driver currently. DSA will provide the needed 6062306a36Sopenharmony_cidevice_node pointers which are then accessible by the switch driver setup 6162306a36Sopenharmony_cifunction to setup resources such as register ranges and interrupts. This 6262306a36Sopenharmony_cicurrently works very well because none of the of_* functions utilized by the 6362306a36Sopenharmony_cidriver require a struct device to be bound to a struct device_node, but things 6462306a36Sopenharmony_cimay change in the future. 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ciMDIO indirect accesses 6762306a36Sopenharmony_ci---------------------- 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ciDue to a limitation in how Broadcom switches have been designed, external 7062306a36Sopenharmony_ciBroadcom switches connected to a SF2 require the use of the DSA slave MDIO bus 7162306a36Sopenharmony_ciin order to properly configure them. By default, the SF2 pseudo-PHY address, and 7262306a36Sopenharmony_cian external switch pseudo-PHY address will both be snooping for incoming MDIO 7362306a36Sopenharmony_citransactions, since they are at the same address (30), resulting in some kind of 7462306a36Sopenharmony_ci"double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we 7562306a36Sopenharmony_ciselectively divert reads and writes towards external Broadcom switches 7662306a36Sopenharmony_cipseudo-PHY addresses. Newer revisions of the SF2 hardware have introduced a 7762306a36Sopenharmony_ciconfigurable pseudo-PHY address which circumvents the initial design limitation. 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ciMultimedia over CoAxial (MoCA) interfaces 8062306a36Sopenharmony_ci----------------------------------------- 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ciMoCA interfaces are fairly specific and require the use of a firmware blob which 8362306a36Sopenharmony_cigets loaded onto the MoCA processor(s) for packet processing. The switch 8462306a36Sopenharmony_cihardware contains logic which will assert/de-assert link states accordingly for 8562306a36Sopenharmony_cithe MoCA interface whenever the MoCA coaxial cable gets disconnected or the 8662306a36Sopenharmony_cifirmware gets reloaded. The SF2 driver relies on such events to properly set its 8762306a36Sopenharmony_ciMoCA interface carrier state and properly report this to the networking stack. 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ciThe MoCA interfaces are supported using the PHY library's fixed PHY/emulated PHY 9062306a36Sopenharmony_cidevice and the switch driver registers a ``fixed_link_update`` callback for such 9162306a36Sopenharmony_ciPHYs which reflects the link state obtained from the interrupt handler. 9262306a36Sopenharmony_ci 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ciPower Management 9562306a36Sopenharmony_ci---------------- 9662306a36Sopenharmony_ci 9762306a36Sopenharmony_ciWhenever possible, the SF2 driver tries to minimize the overall switch power 9862306a36Sopenharmony_ciconsumption by applying a combination of: 9962306a36Sopenharmony_ci 10062306a36Sopenharmony_ci- turning off internal buffers/memories 10162306a36Sopenharmony_ci- disabling packet processing logic 10262306a36Sopenharmony_ci- putting integrated PHYs in IDDQ/low-power 10362306a36Sopenharmony_ci- reducing the switch core clock based on the active port count 10462306a36Sopenharmony_ci- enabling and advertising EEE 10562306a36Sopenharmony_ci- turning off RGMII data processing logic when the link goes down 10662306a36Sopenharmony_ci 10762306a36Sopenharmony_ciWake-on-LAN 10862306a36Sopenharmony_ci----------- 10962306a36Sopenharmony_ci 11062306a36Sopenharmony_ciWake-on-LAN is currently implemented by utilizing the host processor Ethernet 11162306a36Sopenharmony_ciMAC controller wake-on logic. Whenever Wake-on-LAN is requested, an intersection 11262306a36Sopenharmony_cibetween the user request and the supported host Ethernet interface WoL 11362306a36Sopenharmony_cicapabilities is done and the intersection result gets configured. During 11462306a36Sopenharmony_cisystem-wide suspend/resume, only ports not participating in Wake-on-LAN are 11562306a36Sopenharmony_cidisabled. 116