162306a36Sopenharmony_ci===================================== 262306a36Sopenharmony_ciLinux I2C slave interface description 362306a36Sopenharmony_ci===================================== 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciby Wolfram Sang <wsa@sang-engineering.com> in 2014-15 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciLinux can also be an I2C slave if the I2C controller in use has slave 862306a36Sopenharmony_cifunctionality. For that to work, one needs slave support in the bus driver plus 962306a36Sopenharmony_cia hardware independent software backend providing the actual functionality. An 1062306a36Sopenharmony_ciexample for the latter is the slave-eeprom driver, which acts as a dual memory 1162306a36Sopenharmony_cidriver. While another I2C master on the bus can access it like a regular 1262306a36Sopenharmony_ciEEPROM, the Linux I2C slave can access the content via sysfs and handle data as 1362306a36Sopenharmony_cineeded. The backend driver and the I2C bus driver communicate via events. Here 1462306a36Sopenharmony_ciis a small graph visualizing the data flow and the means by which data is 1562306a36Sopenharmony_citransported. The dotted line marks only one example. The backend could also 1662306a36Sopenharmony_ciuse a character device, be in-kernel only, or something completely different:: 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci e.g. sysfs I2C slave events I/O registers 2062306a36Sopenharmony_ci +-----------+ v +---------+ v +--------+ v +------------+ 2162306a36Sopenharmony_ci | Userspace +........+ Backend +-----------+ Driver +-----+ Controller | 2262306a36Sopenharmony_ci +-----------+ +---------+ +--------+ +------------+ 2362306a36Sopenharmony_ci | | 2462306a36Sopenharmony_ci ----------------------------------------------------------------+-- I2C 2562306a36Sopenharmony_ci --------------------------------------------------------------+---- Bus 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ciNote: Technically, there is also the I2C core between the backend and the 2862306a36Sopenharmony_cidriver. However, at this time of writing, the layer is transparent. 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ciUser manual 3262306a36Sopenharmony_ci=========== 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ciI2C slave backends behave like standard I2C clients. So, you can instantiate 3562306a36Sopenharmony_cithem as described in the document instantiating-devices.rst. The only 3662306a36Sopenharmony_cidifference is that i2c slave backends have their own address space. So, you 3762306a36Sopenharmony_cihave to add 0x1000 to the address you would originally request. An example for 3862306a36Sopenharmony_ciinstantiating the slave-eeprom driver from userspace at the 7 bit address 0x64 3962306a36Sopenharmony_cion bus 1:: 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci # echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-1/new_device 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ciEach backend should come with separate documentation to describe its specific 4462306a36Sopenharmony_cibehaviour and setup. 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ciDeveloper manual 4862306a36Sopenharmony_ci================ 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_ciFirst, the events which are used by the bus driver and the backend will be 5162306a36Sopenharmony_cidescribed in detail. After that, some implementation hints for extending bus 5262306a36Sopenharmony_cidrivers and writing backends will be given. 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciI2C slave events 5662306a36Sopenharmony_ci---------------- 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ciThe bus driver sends an event to the backend using the following function:: 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci ret = i2c_slave_event(client, event, &val) 6162306a36Sopenharmony_ci 6262306a36Sopenharmony_ci'client' describes the I2C slave device. 'event' is one of the special event 6362306a36Sopenharmony_citypes described hereafter. 'val' holds an u8 value for the data byte to be 6462306a36Sopenharmony_ciread/written and is thus bidirectional. The pointer to val must always be 6562306a36Sopenharmony_ciprovided even if val is not used for an event, i.e. don't use NULL here. 'ret' 6662306a36Sopenharmony_ciis the return value from the backend. Mandatory events must be provided by the 6762306a36Sopenharmony_cibus drivers and must be checked for by backend drivers. 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ciEvent types: 7062306a36Sopenharmony_ci 7162306a36Sopenharmony_ci* I2C_SLAVE_WRITE_REQUESTED (mandatory) 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci 'val': unused 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci 'ret': 0 if the backend is ready, otherwise some errno 7662306a36Sopenharmony_ci 7762306a36Sopenharmony_ciAnother I2C master wants to write data to us. This event should be sent once 7862306a36Sopenharmony_ciour own address and the write bit was detected. The data did not arrive yet, so 7962306a36Sopenharmony_cithere is nothing to process or return. After returning, the bus driver must 8062306a36Sopenharmony_cialways ack the address phase. If 'ret' is zero, backend initialization or 8162306a36Sopenharmony_ciwakeup is done and further data may be received. If 'ret' is an errno, the bus 8262306a36Sopenharmony_cidriver should nack all incoming bytes until the next stop condition to enforce 8362306a36Sopenharmony_cia retry of the transmission. 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci* I2C_SLAVE_READ_REQUESTED (mandatory) 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_ci 'val': backend returns first byte to be sent 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ci 'ret': always 0 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_ciAnother I2C master wants to read data from us. This event should be sent once 9262306a36Sopenharmony_ciour own address and the read bit was detected. After returning, the bus driver 9362306a36Sopenharmony_cishould transmit the first byte. 9462306a36Sopenharmony_ci 9562306a36Sopenharmony_ci* I2C_SLAVE_WRITE_RECEIVED (mandatory) 9662306a36Sopenharmony_ci 9762306a36Sopenharmony_ci 'val': bus driver delivers received byte 9862306a36Sopenharmony_ci 9962306a36Sopenharmony_ci 'ret': 0 if the byte should be acked, some errno if the byte should be nacked 10062306a36Sopenharmony_ci 10162306a36Sopenharmony_ciAnother I2C master has sent a byte to us which needs to be set in 'val'. If 'ret' 10262306a36Sopenharmony_ciis zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte 10362306a36Sopenharmony_cishould be nacked. 10462306a36Sopenharmony_ci 10562306a36Sopenharmony_ci* I2C_SLAVE_READ_PROCESSED (mandatory) 10662306a36Sopenharmony_ci 10762306a36Sopenharmony_ci 'val': backend returns next byte to be sent 10862306a36Sopenharmony_ci 10962306a36Sopenharmony_ci 'ret': always 0 11062306a36Sopenharmony_ci 11162306a36Sopenharmony_ciThe bus driver requests the next byte to be sent to another I2C master in 11262306a36Sopenharmony_ci'val'. Important: This does not mean that the previous byte has been acked, it 11362306a36Sopenharmony_cionly means that the previous byte is shifted out to the bus! To ensure seamless 11462306a36Sopenharmony_citransmission, most hardware requests the next byte when the previous one is 11562306a36Sopenharmony_cistill shifted out. If the master sends NACK and stops reading after the byte 11662306a36Sopenharmony_cicurrently shifted out, this byte requested here is never used. It very likely 11762306a36Sopenharmony_cineeds to be sent again on the next I2C_SLAVE_READ_REQUEST, depending a bit on 11862306a36Sopenharmony_ciyour backend, though. 11962306a36Sopenharmony_ci 12062306a36Sopenharmony_ci* I2C_SLAVE_STOP (mandatory) 12162306a36Sopenharmony_ci 12262306a36Sopenharmony_ci 'val': unused 12362306a36Sopenharmony_ci 12462306a36Sopenharmony_ci 'ret': always 0 12562306a36Sopenharmony_ci 12662306a36Sopenharmony_ciA stop condition was received. This can happen anytime and the backend should 12762306a36Sopenharmony_cireset its state machine for I2C transfers to be able to receive new requests. 12862306a36Sopenharmony_ci 12962306a36Sopenharmony_ci 13062306a36Sopenharmony_ciSoftware backends 13162306a36Sopenharmony_ci----------------- 13262306a36Sopenharmony_ci 13362306a36Sopenharmony_ciIf you want to write a software backend: 13462306a36Sopenharmony_ci 13562306a36Sopenharmony_ci* use a standard i2c_driver and its matching mechanisms 13662306a36Sopenharmony_ci* write the slave_callback which handles the above slave events 13762306a36Sopenharmony_ci (best using a state machine) 13862306a36Sopenharmony_ci* register this callback via i2c_slave_register() 13962306a36Sopenharmony_ci 14062306a36Sopenharmony_ciCheck the i2c-slave-eeprom driver as an example. 14162306a36Sopenharmony_ci 14262306a36Sopenharmony_ci 14362306a36Sopenharmony_ciBus driver support 14462306a36Sopenharmony_ci------------------ 14562306a36Sopenharmony_ci 14662306a36Sopenharmony_ciIf you want to add slave support to the bus driver: 14762306a36Sopenharmony_ci 14862306a36Sopenharmony_ci* implement calls to register/unregister the slave and add those to the 14962306a36Sopenharmony_ci struct i2c_algorithm. When registering, you probably need to set the I2C 15062306a36Sopenharmony_ci slave address and enable slave specific interrupts. If you use runtime pm, you 15162306a36Sopenharmony_ci should use pm_runtime_get_sync() because your device usually needs to be 15262306a36Sopenharmony_ci powered on always to be able to detect its slave address. When unregistering, 15362306a36Sopenharmony_ci do the inverse of the above. 15462306a36Sopenharmony_ci 15562306a36Sopenharmony_ci* Catch the slave interrupts and send appropriate i2c_slave_events to the backend. 15662306a36Sopenharmony_ci 15762306a36Sopenharmony_ciNote that most hardware supports being master _and_ slave on the same bus. So, 15862306a36Sopenharmony_ciif you extend a bus driver, please make sure that the driver supports that as 15962306a36Sopenharmony_ciwell. In almost all cases, slave support does not need to disable the master 16062306a36Sopenharmony_cifunctionality. 16162306a36Sopenharmony_ci 16262306a36Sopenharmony_ciCheck the i2c-rcar driver as an example. 16362306a36Sopenharmony_ci 16462306a36Sopenharmony_ci 16562306a36Sopenharmony_ciAbout ACK/NACK 16662306a36Sopenharmony_ci-------------- 16762306a36Sopenharmony_ci 16862306a36Sopenharmony_ciIt is good behaviour to always ACK the address phase, so the master knows if a 16962306a36Sopenharmony_cidevice is basically present or if it mysteriously disappeared. Using NACK to 17062306a36Sopenharmony_cistate being busy is troublesome. SMBus demands to always ACK the address phase, 17162306a36Sopenharmony_ciwhile the I2C specification is more loose on that. Most I2C controllers also 17262306a36Sopenharmony_ciautomatically ACK when detecting their slave addresses, so there is no option 17362306a36Sopenharmony_cito NACK them. For those reasons, this API does not support NACK in the address 17462306a36Sopenharmony_ciphase. 17562306a36Sopenharmony_ci 17662306a36Sopenharmony_ciCurrently, there is no slave event to report if the master did ACK or NACK a 17762306a36Sopenharmony_cibyte when it reads from us. We could make this an optional event if the need 17862306a36Sopenharmony_ciarises. However, cases should be extremely rare because the master is expected 17962306a36Sopenharmony_cito send STOP after that and we have an event for that. Also, keep in mind not 18062306a36Sopenharmony_ciall I2C controllers have the possibility to report that event. 18162306a36Sopenharmony_ci 18262306a36Sopenharmony_ci 18362306a36Sopenharmony_ciAbout buffers 18462306a36Sopenharmony_ci------------- 18562306a36Sopenharmony_ci 18662306a36Sopenharmony_ciDuring development of this API, the question of using buffers instead of just 18762306a36Sopenharmony_cibytes came up. Such an extension might be possible, usefulness is unclear at 18862306a36Sopenharmony_cithis time of writing. Some points to keep in mind when using buffers: 18962306a36Sopenharmony_ci 19062306a36Sopenharmony_ci* Buffers should be opt-in and backend drivers will always have to support 19162306a36Sopenharmony_ci byte-based transactions as the ultimate fallback anyhow because this is how 19262306a36Sopenharmony_ci the majority of HW works. 19362306a36Sopenharmony_ci 19462306a36Sopenharmony_ci* For backends simulating hardware registers, buffers are largely not helpful 19562306a36Sopenharmony_ci because after each byte written an action should be immediately triggered. 19662306a36Sopenharmony_ci For reads, the data kept in the buffer might get stale if the backend just 19762306a36Sopenharmony_ci updated a register because of internal processing. 19862306a36Sopenharmony_ci 19962306a36Sopenharmony_ci* A master can send STOP at any time. For partially transferred buffers, this 20062306a36Sopenharmony_ci means additional code to handle this exception. Such code tends to be 20162306a36Sopenharmony_ci error-prone. 202