162306a36Sopenharmony_ci================
262306a36Sopenharmony_ciThe I2C Protocol
362306a36Sopenharmony_ci================
462306a36Sopenharmony_ci
562306a36Sopenharmony_ciThis document is an overview of the basic I2C transactions and the kernel
662306a36Sopenharmony_ciAPIs to perform them.
762306a36Sopenharmony_ci
862306a36Sopenharmony_ciKey to symbols
962306a36Sopenharmony_ci==============
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci=============== =============================================================
1262306a36Sopenharmony_ciS               Start condition
1362306a36Sopenharmony_ciP               Stop condition
1462306a36Sopenharmony_ciRd/Wr (1 bit)   Read/Write bit. Rd equals 1, Wr equals 0.
1562306a36Sopenharmony_ciA, NA (1 bit)   Acknowledge (ACK) and Not Acknowledge (NACK) bit
1662306a36Sopenharmony_ciAddr  (7 bits)  I2C 7 bit address. Note that this can be expanded to
1762306a36Sopenharmony_ci                get a 10 bit I2C address.
1862306a36Sopenharmony_ciData  (8 bits)  A plain data byte.
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci[..]            Data sent by I2C device, as opposed to data sent by the
2162306a36Sopenharmony_ci                host adapter.
2262306a36Sopenharmony_ci=============== =============================================================
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ciSimple send transaction
2662306a36Sopenharmony_ci=======================
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ciImplemented by i2c_master_send()::
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci  S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ciSimple receive transaction
3462306a36Sopenharmony_ci==========================
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ciImplemented by i2c_master_recv()::
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci  S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ciCombined transactions
4262306a36Sopenharmony_ci=====================
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_ciImplemented by i2c_transfer().
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ciThey are just like the above transactions, but instead of a stop
4762306a36Sopenharmony_cicondition P a start condition S is sent and the transaction continues.
4862306a36Sopenharmony_ciAn example of a byte read, followed by a byte write::
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci  S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ciModified transactions
5462306a36Sopenharmony_ci=====================
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ciThe following modifications to the I2C protocol can also be generated by
5762306a36Sopenharmony_cisetting these flags for I2C messages. With the exception of I2C_M_NOSTART, they
5862306a36Sopenharmony_ciare usually only needed to work around device issues:
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ciI2C_M_IGNORE_NAK:
6162306a36Sopenharmony_ci    Normally message is interrupted immediately if there is [NA] from the
6262306a36Sopenharmony_ci    client. Setting this flag treats any [NA] as [A], and all of
6362306a36Sopenharmony_ci    message is sent.
6462306a36Sopenharmony_ci    These messages may still fail to SCL lo->hi timeout.
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ciI2C_M_NO_RD_ACK:
6762306a36Sopenharmony_ci    In a read message, master A/NA bit is skipped.
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ciI2C_M_NOSTART:
7062306a36Sopenharmony_ci    In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
7162306a36Sopenharmony_ci    point. For example, setting I2C_M_NOSTART on the second partial message
7262306a36Sopenharmony_ci    generates something like::
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ci      S Addr Rd [A] [Data] NA Data [A] P
7562306a36Sopenharmony_ci
7662306a36Sopenharmony_ci    If you set the I2C_M_NOSTART variable for the first partial message,
7762306a36Sopenharmony_ci    we do not generate Addr, but we do generate the start condition S.
7862306a36Sopenharmony_ci    This will probably confuse all other clients on your bus, so don't
7962306a36Sopenharmony_ci    try this.
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ci    This is often used to gather transmits from multiple data buffers in
8262306a36Sopenharmony_ci    system memory into something that appears as a single transfer to the
8362306a36Sopenharmony_ci    I2C device but may also be used between direction changes by some
8462306a36Sopenharmony_ci    rare devices.
8562306a36Sopenharmony_ci
8662306a36Sopenharmony_ciI2C_M_REV_DIR_ADDR:
8762306a36Sopenharmony_ci    This toggles the Rd/Wr flag. That is, if you want to do a write, but
8862306a36Sopenharmony_ci    need to emit an Rd instead of a Wr, or vice versa, you set this
8962306a36Sopenharmony_ci    flag. For example::
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_ci      S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
9262306a36Sopenharmony_ci
9362306a36Sopenharmony_ciI2C_M_STOP:
9462306a36Sopenharmony_ci    Force a stop condition (P) after the message. Some I2C related protocols
9562306a36Sopenharmony_ci    like SCCB require that. Normally, you really don't want to get interrupted
9662306a36Sopenharmony_ci    between the messages of one transfer.
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