162306a36Sopenharmony_ci================== 262306a36Sopenharmony_ciDriver i2c-mlxcpld 362306a36Sopenharmony_ci================== 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciAuthor: Michael Shych <michaelsh@mellanox.com> 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciThis is the Mellanox I2C controller logic, implemented in Lattice CPLD 862306a36Sopenharmony_cidevice. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciDevice supports: 1162306a36Sopenharmony_ci - Master mode. 1262306a36Sopenharmony_ci - One physical bus. 1362306a36Sopenharmony_ci - Polling mode. 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ciThis controller is equipped within the next Mellanox systems: 1662306a36Sopenharmony_ci"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", 1762306a36Sopenharmony_ci"msn2740", "msn2100". 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciThe next transaction types are supported: 2062306a36Sopenharmony_ci - Receive Byte/Block. 2162306a36Sopenharmony_ci - Send Byte/Block. 2262306a36Sopenharmony_ci - Read Byte/Block. 2362306a36Sopenharmony_ci - Write Byte/Block. 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ciRegisters: 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci=============== === ======================================================================= 2862306a36Sopenharmony_ciCPBLTY 0x0 - capability reg. 2962306a36Sopenharmony_ci Bits [6:5] - transaction length. b01 - 72B is supported, 3062306a36Sopenharmony_ci 36B in other case. 3162306a36Sopenharmony_ci Bit 7 - SMBus block read support. 3262306a36Sopenharmony_ciCTRL 0x1 - control reg. 3362306a36Sopenharmony_ci Resets all the registers. 3462306a36Sopenharmony_ciHALF_CYC 0x4 - cycle reg. 3562306a36Sopenharmony_ci Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK 3662306a36Sopenharmony_ci units). 3762306a36Sopenharmony_ciI2C_HOLD 0x5 - hold reg. 3862306a36Sopenharmony_ci OE (output enable) is delayed by value set to this register 3962306a36Sopenharmony_ci (in LPC_CLK units) 4062306a36Sopenharmony_ciCMD 0x6 - command reg. 4162306a36Sopenharmony_ci Bit 0, 0 = write, 1 = read. 4262306a36Sopenharmony_ci Bits [7:1] - the 7bit Address of the I2C device. 4362306a36Sopenharmony_ci It should be written last as it triggers an I2C transaction. 4462306a36Sopenharmony_ciNUM_DATA 0x7 - data size reg. 4562306a36Sopenharmony_ci Number of data bytes to write in read transaction 4662306a36Sopenharmony_ciNUM_ADDR 0x8 - address reg. 4762306a36Sopenharmony_ci Number of address bytes to write in read transaction. 4862306a36Sopenharmony_ciSTATUS 0x9 - status reg. 4962306a36Sopenharmony_ci Bit 0 - transaction is completed. 5062306a36Sopenharmony_ci Bit 4 - ACK/NACK. 5162306a36Sopenharmony_ciDATAx 0xa - 0x54 - 68 bytes data buffer regs. 5262306a36Sopenharmony_ci For write transaction address is specified in four first bytes 5362306a36Sopenharmony_ci (DATA1 - DATA4), data starting from DATA4. 5462306a36Sopenharmony_ci For read transactions address is sent in a separate transaction and 5562306a36Sopenharmony_ci specified in the four first bytes (DATA0 - DATA3). Data is read 5662306a36Sopenharmony_ci starting from DATA0. 5762306a36Sopenharmony_ci=============== === ======================================================================= 58