162306a36Sopenharmony_ciCavium SuperSpeed DWC3 USB SoC controller 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- compatible: Should contain "cavium,octeon-7130-usb-uctl" 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciRequired child node: 762306a36Sopenharmony_ciA child node must exist to represent the core DWC3 IP block. The name of 862306a36Sopenharmony_cithe node is not important. The content of the node is defined in dwc3.txt. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciExample device node: 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci uctl@1180069000000 { 1362306a36Sopenharmony_ci compatible = "cavium,octeon-7130-usb-uctl"; 1462306a36Sopenharmony_ci reg = <0x00011800 0x69000000 0x00000000 0x00000100>; 1562306a36Sopenharmony_ci ranges; 1662306a36Sopenharmony_ci #address-cells = <0x00000002>; 1762306a36Sopenharmony_ci #size-cells = <0x00000002>; 1862306a36Sopenharmony_ci refclk-frequency = <0x05f5e100>; 1962306a36Sopenharmony_ci refclk-type-ss = "dlmc_ref_clk0"; 2062306a36Sopenharmony_ci refclk-type-hs = "dlmc_ref_clk0"; 2162306a36Sopenharmony_ci power = <0x00000002 0x00000002 0x00000001>; 2262306a36Sopenharmony_ci xhci@1690000000000 { 2362306a36Sopenharmony_ci compatible = "cavium,octeon-7130-xhci", "snps,dwc3"; 2462306a36Sopenharmony_ci reg = <0x00016900 0x00000000 0x00000010 0x00000000>; 2562306a36Sopenharmony_ci interrupt-parent = <0x00000010>; 2662306a36Sopenharmony_ci interrupts = <0x00000009 0x00000004>; 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci }; 29