162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Cadence TTC - Triple Timer Counter 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Michal Simek <michal.simek@amd.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciproperties: 1362306a36Sopenharmony_ci compatible: 1462306a36Sopenharmony_ci const: cdns,ttc 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci reg: 1762306a36Sopenharmony_ci maxItems: 1 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci interrupts: 2062306a36Sopenharmony_ci maxItems: 3 2162306a36Sopenharmony_ci description: | 2262306a36Sopenharmony_ci A list of 3 interrupts; one per timer channel. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci clocks: 2562306a36Sopenharmony_ci maxItems: 1 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci power-domains: 2862306a36Sopenharmony_ci maxItems: 1 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci timer-width: 3162306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32 3262306a36Sopenharmony_ci description: | 3362306a36Sopenharmony_ci Bit width of the timer, necessary if not 16. 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_cirequired: 3662306a36Sopenharmony_ci - compatible 3762306a36Sopenharmony_ci - reg 3862306a36Sopenharmony_ci - interrupts 3962306a36Sopenharmony_ci - clocks 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciadditionalProperties: false 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ciexamples: 4462306a36Sopenharmony_ci - | 4562306a36Sopenharmony_ci ttc0: ttc0@f8001000 { 4662306a36Sopenharmony_ci interrupt-parent = <&intc>; 4762306a36Sopenharmony_ci interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 4862306a36Sopenharmony_ci compatible = "cdns,ttc"; 4962306a36Sopenharmony_ci reg = <0xF8001000 0x1000>; 5062306a36Sopenharmony_ci clocks = <&cpu_clk 3>; 5162306a36Sopenharmony_ci timer-width = <32>; 5262306a36Sopenharmony_ci }; 53