162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: ARM memory mapped architected timer 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Marc Zyngier <marc.zyngier@arm.com> 1162306a36Sopenharmony_ci - Mark Rutland <mark.rutland@arm.com> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cidescription: |+ 1462306a36Sopenharmony_ci ARM cores may have a memory mapped architected timer, which provides up to 8 1562306a36Sopenharmony_ci frames with a physical and optional virtual timer per frame. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs. 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ciproperties: 2062306a36Sopenharmony_ci compatible: 2162306a36Sopenharmony_ci items: 2262306a36Sopenharmony_ci - enum: 2362306a36Sopenharmony_ci - arm,armv7-timer-mem 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci reg: 2662306a36Sopenharmony_ci maxItems: 1 2762306a36Sopenharmony_ci description: The control frame base address 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci '#address-cells': 3062306a36Sopenharmony_ci enum: [1, 2] 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci '#size-cells': 3362306a36Sopenharmony_ci const: 1 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci ranges: true 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci clock-frequency: 3862306a36Sopenharmony_ci description: The frequency of the main counter, in Hz. Should be present 3962306a36Sopenharmony_ci only where necessary to work around broken firmware which does not configure 4062306a36Sopenharmony_ci CNTFRQ on all CPUs to a uniform correct value. Use of this property is 4162306a36Sopenharmony_ci strongly discouraged; fix your firmware unless absolutely impossible. 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci always-on: 4462306a36Sopenharmony_ci type: boolean 4562306a36Sopenharmony_ci description: If present, the timer is powered through an always-on power 4662306a36Sopenharmony_ci domain, therefore it never loses context. 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci arm,cpu-registers-not-fw-configured: 4962306a36Sopenharmony_ci type: boolean 5062306a36Sopenharmony_ci description: Firmware does not initialize any of the generic timer CPU 5162306a36Sopenharmony_ci registers, which contain their architecturally-defined reset values. Only 5262306a36Sopenharmony_ci supported for 32-bit systems which follow the ARMv7 architected reset 5362306a36Sopenharmony_ci values. 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ci arm,no-tick-in-suspend: 5662306a36Sopenharmony_ci type: boolean 5762306a36Sopenharmony_ci description: The main counter does not tick when the system is in 5862306a36Sopenharmony_ci low-power system suspend on some SoCs. This behavior does not match the 5962306a36Sopenharmony_ci Architecture Reference Manual's specification that the system counter "must 6062306a36Sopenharmony_ci be implemented in an always-on power domain." 6162306a36Sopenharmony_ci 6262306a36Sopenharmony_cipatternProperties: 6362306a36Sopenharmony_ci '^frame@[0-9a-z]*$': 6462306a36Sopenharmony_ci type: object 6562306a36Sopenharmony_ci additionalProperties: false 6662306a36Sopenharmony_ci description: A timer node has up to 8 frame sub-nodes, each with the following properties. 6762306a36Sopenharmony_ci properties: 6862306a36Sopenharmony_ci frame-number: 6962306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32 7062306a36Sopenharmony_ci minimum: 0 7162306a36Sopenharmony_ci maximum: 7 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci interrupts: 7462306a36Sopenharmony_ci minItems: 1 7562306a36Sopenharmony_ci items: 7662306a36Sopenharmony_ci - description: physical timer irq 7762306a36Sopenharmony_ci - description: virtual timer irq 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci reg: 8062306a36Sopenharmony_ci minItems: 1 8162306a36Sopenharmony_ci items: 8262306a36Sopenharmony_ci - description: 1st view base address 8362306a36Sopenharmony_ci - description: 2nd optional view base address 8462306a36Sopenharmony_ci 8562306a36Sopenharmony_ci required: 8662306a36Sopenharmony_ci - frame-number 8762306a36Sopenharmony_ci - interrupts 8862306a36Sopenharmony_ci - reg 8962306a36Sopenharmony_ci 9062306a36Sopenharmony_cirequired: 9162306a36Sopenharmony_ci - compatible 9262306a36Sopenharmony_ci - reg 9362306a36Sopenharmony_ci - '#address-cells' 9462306a36Sopenharmony_ci - '#size-cells' 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ciadditionalProperties: false 9762306a36Sopenharmony_ci 9862306a36Sopenharmony_ciexamples: 9962306a36Sopenharmony_ci - | 10062306a36Sopenharmony_ci timer@f0000000 { 10162306a36Sopenharmony_ci compatible = "arm,armv7-timer-mem"; 10262306a36Sopenharmony_ci #address-cells = <1>; 10362306a36Sopenharmony_ci #size-cells = <1>; 10462306a36Sopenharmony_ci ranges = <0 0xf0001000 0x1000>; 10562306a36Sopenharmony_ci reg = <0xf0000000 0x1000>; 10662306a36Sopenharmony_ci clock-frequency = <50000000>; 10762306a36Sopenharmony_ci 10862306a36Sopenharmony_ci frame@0 { 10962306a36Sopenharmony_ci frame-number = <0>; 11062306a36Sopenharmony_ci interrupts = <0 13 0x8>, 11162306a36Sopenharmony_ci <0 14 0x8>; 11262306a36Sopenharmony_ci reg = <0x0000 0x1000>, 11362306a36Sopenharmony_ci <0x1000 0x1000>; 11462306a36Sopenharmony_ci }; 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ci frame@2000 { 11762306a36Sopenharmony_ci frame-number = <1>; 11862306a36Sopenharmony_ci interrupts = <0 15 0x8>; 11962306a36Sopenharmony_ci reg = <0x2000 0x1000>; 12062306a36Sopenharmony_ci }; 12162306a36Sopenharmony_ci }; 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci... 124