162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Peripheral-specific properties for a SPI bus. 862306a36Sopenharmony_ci 962306a36Sopenharmony_cidescription: 1062306a36Sopenharmony_ci Many SPI controllers need to add properties to peripheral devices. They could 1162306a36Sopenharmony_ci be common properties like spi-max-frequency, spi-cpha, etc. or they could be 1262306a36Sopenharmony_ci controller specific like delay in clock or data lines, etc. These properties 1362306a36Sopenharmony_ci need to be defined in the peripheral node because they are per-peripheral and 1462306a36Sopenharmony_ci there can be multiple peripherals attached to a controller. All those 1562306a36Sopenharmony_ci properties are listed here. The controller specific properties should go in 1662306a36Sopenharmony_ci their own separate schema that should be referenced from here. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_cimaintainers: 1962306a36Sopenharmony_ci - Mark Brown <broonie@kernel.org> 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ciproperties: 2262306a36Sopenharmony_ci reg: 2362306a36Sopenharmony_ci minItems: 1 2462306a36Sopenharmony_ci maxItems: 256 2562306a36Sopenharmony_ci items: 2662306a36Sopenharmony_ci items: 2762306a36Sopenharmony_ci - minimum: 0 2862306a36Sopenharmony_ci maximum: 256 2962306a36Sopenharmony_ci description: 3062306a36Sopenharmony_ci Chip select used by the device. 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci spi-cs-high: 3362306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/flag 3462306a36Sopenharmony_ci description: 3562306a36Sopenharmony_ci The device requires the chip select active high. 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci spi-lsb-first: 3862306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/flag 3962306a36Sopenharmony_ci description: 4062306a36Sopenharmony_ci The device requires the LSB first mode. 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci spi-max-frequency: 4362306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32 4462306a36Sopenharmony_ci description: 4562306a36Sopenharmony_ci Maximum SPI clocking speed of the device in Hz. 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci spi-cs-setup-delay-ns: 4862306a36Sopenharmony_ci description: 4962306a36Sopenharmony_ci Delay in nanoseconds to be introduced by the controller after CS is 5062306a36Sopenharmony_ci asserted. 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci spi-cs-hold-delay-ns: 5362306a36Sopenharmony_ci description: 5462306a36Sopenharmony_ci Delay in nanoseconds to be introduced by the controller before CS is 5562306a36Sopenharmony_ci de-asserted. 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci spi-cs-inactive-delay-ns: 5862306a36Sopenharmony_ci description: 5962306a36Sopenharmony_ci Delay in nanoseconds to be introduced by the controller after CS is 6062306a36Sopenharmony_ci de-asserted. 6162306a36Sopenharmony_ci 6262306a36Sopenharmony_ci spi-rx-bus-width: 6362306a36Sopenharmony_ci description: 6462306a36Sopenharmony_ci Bus width to the SPI bus used for read transfers. 6562306a36Sopenharmony_ci If 0 is provided, then no RX will be possible on this device. 6662306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32 6762306a36Sopenharmony_ci enum: [0, 1, 2, 4, 8] 6862306a36Sopenharmony_ci default: 1 6962306a36Sopenharmony_ci 7062306a36Sopenharmony_ci spi-rx-delay-us: 7162306a36Sopenharmony_ci description: 7262306a36Sopenharmony_ci Delay, in microseconds, after a read transfer. 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci rx-sample-delay-ns: 7562306a36Sopenharmony_ci description: SPI Rx sample delay offset, unit is nanoseconds. 7662306a36Sopenharmony_ci The delay from the default sample time before the actual 7762306a36Sopenharmony_ci sample of the rxd input signal occurs. 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci spi-tx-bus-width: 8062306a36Sopenharmony_ci description: 8162306a36Sopenharmony_ci Bus width to the SPI bus used for write transfers. 8262306a36Sopenharmony_ci If 0 is provided, then no TX will be possible on this device. 8362306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32 8462306a36Sopenharmony_ci enum: [0, 1, 2, 4, 8] 8562306a36Sopenharmony_ci default: 1 8662306a36Sopenharmony_ci 8762306a36Sopenharmony_ci spi-tx-delay-us: 8862306a36Sopenharmony_ci description: 8962306a36Sopenharmony_ci Delay, in microseconds, after a write transfer. 9062306a36Sopenharmony_ci 9162306a36Sopenharmony_ci stacked-memories: 9262306a36Sopenharmony_ci description: Several SPI memories can be wired in stacked mode. 9362306a36Sopenharmony_ci This basically means that either a device features several chip 9462306a36Sopenharmony_ci selects, or that different devices must be seen as a single 9562306a36Sopenharmony_ci bigger chip. This basically doubles (or more) the total address 9662306a36Sopenharmony_ci space with only a single additional wire, while still needing 9762306a36Sopenharmony_ci to repeat the commands when crossing a chip boundary. The size of 9862306a36Sopenharmony_ci each chip should be provided as members of the array. 9962306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint64-array 10062306a36Sopenharmony_ci minItems: 2 10162306a36Sopenharmony_ci maxItems: 4 10262306a36Sopenharmony_ci 10362306a36Sopenharmony_ci parallel-memories: 10462306a36Sopenharmony_ci description: Several SPI memories can be wired in parallel mode. 10562306a36Sopenharmony_ci The devices are physically on a different buses but will always 10662306a36Sopenharmony_ci act synchronously as each data word is spread across the 10762306a36Sopenharmony_ci different memories (eg. even bits are stored in one memory, odd 10862306a36Sopenharmony_ci bits in the other). This basically doubles the address space and 10962306a36Sopenharmony_ci the throughput while greatly complexifying the wiring because as 11062306a36Sopenharmony_ci many busses as devices must be wired. The size of each chip should 11162306a36Sopenharmony_ci be provided as members of the array. 11262306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint64-array 11362306a36Sopenharmony_ci minItems: 2 11462306a36Sopenharmony_ci maxItems: 4 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ci# The controller specific properties go here. 11762306a36Sopenharmony_ciallOf: 11862306a36Sopenharmony_ci - $ref: cdns,qspi-nor-peripheral-props.yaml# 11962306a36Sopenharmony_ci - $ref: samsung,spi-peripheral-props.yaml# 12062306a36Sopenharmony_ci - $ref: nvidia,tegra210-quad-peripheral-props.yaml# 12162306a36Sopenharmony_ci 12262306a36Sopenharmony_ciadditionalProperties: true 123