162306a36Sopenharmony_ci* Marvell Armada 3700 SPI Controller 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired Properties: 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci- compatible: should be "marvell,armada-3700-spi" 662306a36Sopenharmony_ci- reg: physical base address of the controller and length of memory mapped 762306a36Sopenharmony_ci region. 862306a36Sopenharmony_ci- interrupts: The interrupt number. The interrupt specifier format depends on 962306a36Sopenharmony_ci the interrupt controller and of its driver. 1062306a36Sopenharmony_ci- clocks: Must contain the clock source, usually from the North Bridge clocks. 1162306a36Sopenharmony_ci- num-cs: The number of chip selects that is supported by this SPI Controller 1262306a36Sopenharmony_ci- #address-cells: should be 1. 1362306a36Sopenharmony_ci- #size-cells: should be 0. 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ciExample: 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci spi0: spi@10600 { 1862306a36Sopenharmony_ci compatible = "marvell,armada-3700-spi"; 1962306a36Sopenharmony_ci #address-cells = <1>; 2062306a36Sopenharmony_ci #size-cells = <0>; 2162306a36Sopenharmony_ci reg = <0x10600 0x5d>; 2262306a36Sopenharmony_ci clocks = <&nb_perih_clk 7>; 2362306a36Sopenharmony_ci interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2462306a36Sopenharmony_ci num-cs = <4>; 2562306a36Sopenharmony_ci }; 26