162306a36Sopenharmony_ci* SPI (Serial Peripheral Interface) 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- cell-index : QE SPI subblock index. 562306a36Sopenharmony_ci 0: QE subblock SPI1 662306a36Sopenharmony_ci 1: QE subblock SPI2 762306a36Sopenharmony_ci- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 862306a36Sopenharmony_ci- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 962306a36Sopenharmony_ci- reg : Offset and length of the register set for the device 1062306a36Sopenharmony_ci- interrupts : <a b> where a is the interrupt number and b is a 1162306a36Sopenharmony_ci field that represents an encoding of the sense and level 1262306a36Sopenharmony_ci information for the interrupt. This should be encoded based on 1362306a36Sopenharmony_ci the information in section 2) depending on the type of interrupt 1462306a36Sopenharmony_ci controller you have. 1562306a36Sopenharmony_ci- clock-frequency : input clock frequency to non FSL_SOC cores 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ciOptional properties: 1862306a36Sopenharmony_ci- cs-gpios : specifies the gpio pins to be used for chipselects. 1962306a36Sopenharmony_ci The gpios will be referred to as reg = <index> in the SPI child nodes. 2062306a36Sopenharmony_ci If unspecified, a single SPI device without a chip select can be used. 2162306a36Sopenharmony_ci- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the 2262306a36Sopenharmony_ci SPISEL_BOOT signal is used as chip select for a slave device. Use 2362306a36Sopenharmony_ci reg = <number of gpios> in the corresponding child node, i.e. 0 if 2462306a36Sopenharmony_ci the cs-gpios property is not present. 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ciExample: 2762306a36Sopenharmony_ci spi@4c0 { 2862306a36Sopenharmony_ci cell-index = <0>; 2962306a36Sopenharmony_ci compatible = "fsl,spi"; 3062306a36Sopenharmony_ci reg = <4c0 40>; 3162306a36Sopenharmony_ci interrupts = <82 0>; 3262306a36Sopenharmony_ci interrupt-parent = <700>; 3362306a36Sopenharmony_ci mode = "cpu"; 3462306a36Sopenharmony_ci cs-gpios = <&gpio 18 1 // device reg=<0> 3562306a36Sopenharmony_ci &gpio 19 1>; // device reg=<1> 3662306a36Sopenharmony_ci }; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci* eSPI (Enhanced Serial Peripheral Interface) 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciRequired properties: 4262306a36Sopenharmony_ci- compatible : should be "fsl,mpc8536-espi". 4362306a36Sopenharmony_ci- reg : Offset and length of the register set for the device. 4462306a36Sopenharmony_ci- interrupts : should contain eSPI interrupt, the device has one interrupt. 4562306a36Sopenharmony_ci- fsl,espi-num-chipselects : the number of the chipselect signals. 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ciOptional properties: 4862306a36Sopenharmony_ci- fsl,csbef: chip select assertion time in bits before frame starts 4962306a36Sopenharmony_ci- fsl,csaft: chip select negation time in bits after frame ends 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ciExample: 5262306a36Sopenharmony_ci spi@110000 { 5362306a36Sopenharmony_ci #address-cells = <1>; 5462306a36Sopenharmony_ci #size-cells = <0>; 5562306a36Sopenharmony_ci compatible = "fsl,mpc8536-espi"; 5662306a36Sopenharmony_ci reg = <0x110000 0x1000>; 5762306a36Sopenharmony_ci interrupts = <53 0x2>; 5862306a36Sopenharmony_ci interrupt-parent = <&mpic>; 5962306a36Sopenharmony_ci fsl,espi-num-chipselects = <4>; 6062306a36Sopenharmony_ci fsl,csbef = <1>; 6162306a36Sopenharmony_ci fsl,csaft = <1>; 6262306a36Sopenharmony_ci }; 63