162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: GENI Serial Engine QUP Wrapper Controller 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Bjorn Andersson <bjorn.andersson@linaro.org> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: | 1362306a36Sopenharmony_ci Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper 1462306a36Sopenharmony_ci is a programmable module for supporting a wide range of serial interfaces 1562306a36Sopenharmony_ci like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial 1662306a36Sopenharmony_ci Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP 1762306a36Sopenharmony_ci Wrapper controller is modeled as a node with zero or more child nodes each 1862306a36Sopenharmony_ci representing a serial engine. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciproperties: 2162306a36Sopenharmony_ci compatible: 2262306a36Sopenharmony_ci enum: 2362306a36Sopenharmony_ci - qcom,geni-se-qup 2462306a36Sopenharmony_ci - qcom,geni-se-i2c-master-hub 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci reg: 2762306a36Sopenharmony_ci description: QUP wrapper common register address and length. 2862306a36Sopenharmony_ci maxItems: 1 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci clock-names: 3162306a36Sopenharmony_ci minItems: 1 3262306a36Sopenharmony_ci maxItems: 2 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci clocks: 3562306a36Sopenharmony_ci minItems: 1 3662306a36Sopenharmony_ci maxItems: 2 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci "#address-cells": 3962306a36Sopenharmony_ci const: 2 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci "#size-cells": 4262306a36Sopenharmony_ci const: 2 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci ranges: true 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci interconnects: 4762306a36Sopenharmony_ci maxItems: 1 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_ci interconnect-names: 5062306a36Sopenharmony_ci const: qup-core 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ci iommus: 5362306a36Sopenharmony_ci maxItems: 1 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_cirequired: 5662306a36Sopenharmony_ci - compatible 5762306a36Sopenharmony_ci - reg 5862306a36Sopenharmony_ci - clock-names 5962306a36Sopenharmony_ci - clocks 6062306a36Sopenharmony_ci - "#address-cells" 6162306a36Sopenharmony_ci - "#size-cells" 6262306a36Sopenharmony_ci - ranges 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_cipatternProperties: 6562306a36Sopenharmony_ci "spi@[0-9a-f]+$": 6662306a36Sopenharmony_ci type: object 6762306a36Sopenharmony_ci description: GENI serial engine based SPI controller. SPI in master mode 6862306a36Sopenharmony_ci supports up to 50MHz, up to four chip selects, programmable 6962306a36Sopenharmony_ci data path from 4 bits to 32 bits and numerous protocol 7062306a36Sopenharmony_ci variants. 7162306a36Sopenharmony_ci $ref: /schemas/spi/qcom,spi-geni-qcom.yaml# 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ci "i2c@[0-9a-f]+$": 7462306a36Sopenharmony_ci type: object 7562306a36Sopenharmony_ci description: GENI serial engine based I2C controller. 7662306a36Sopenharmony_ci $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml# 7762306a36Sopenharmony_ci 7862306a36Sopenharmony_ci "serial@[0-9a-f]+$": 7962306a36Sopenharmony_ci type: object 8062306a36Sopenharmony_ci description: GENI Serial Engine based UART Controller. 8162306a36Sopenharmony_ci $ref: /schemas/serial/qcom,serial-geni-qcom.yaml# 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ciallOf: 8462306a36Sopenharmony_ci - if: 8562306a36Sopenharmony_ci properties: 8662306a36Sopenharmony_ci compatible: 8762306a36Sopenharmony_ci contains: 8862306a36Sopenharmony_ci const: qcom,geni-se-i2c-master-hub 8962306a36Sopenharmony_ci then: 9062306a36Sopenharmony_ci properties: 9162306a36Sopenharmony_ci clock-names: 9262306a36Sopenharmony_ci items: 9362306a36Sopenharmony_ci - const: s-ahb 9462306a36Sopenharmony_ci 9562306a36Sopenharmony_ci clocks: 9662306a36Sopenharmony_ci items: 9762306a36Sopenharmony_ci - description: Slave AHB Clock 9862306a36Sopenharmony_ci 9962306a36Sopenharmony_ci iommus: false 10062306a36Sopenharmony_ci 10162306a36Sopenharmony_ci patternProperties: 10262306a36Sopenharmony_ci "spi@[0-9a-f]+$": false 10362306a36Sopenharmony_ci "serial@[0-9a-f]+$": false 10462306a36Sopenharmony_ci else: 10562306a36Sopenharmony_ci properties: 10662306a36Sopenharmony_ci clock-names: 10762306a36Sopenharmony_ci items: 10862306a36Sopenharmony_ci - const: m-ahb 10962306a36Sopenharmony_ci - const: s-ahb 11062306a36Sopenharmony_ci 11162306a36Sopenharmony_ci clocks: 11262306a36Sopenharmony_ci items: 11362306a36Sopenharmony_ci - description: Master AHB Clock 11462306a36Sopenharmony_ci - description: Slave AHB Clock 11562306a36Sopenharmony_ci 11662306a36Sopenharmony_ciadditionalProperties: false 11762306a36Sopenharmony_ci 11862306a36Sopenharmony_ciexamples: 11962306a36Sopenharmony_ci - | 12062306a36Sopenharmony_ci #include <dt-bindings/clock/qcom,gcc-sdm845.h> 12162306a36Sopenharmony_ci #include <dt-bindings/interrupt-controller/arm-gic.h> 12262306a36Sopenharmony_ci 12362306a36Sopenharmony_ci soc { 12462306a36Sopenharmony_ci #address-cells = <2>; 12562306a36Sopenharmony_ci #size-cells = <2>; 12662306a36Sopenharmony_ci 12762306a36Sopenharmony_ci geniqup@8c0000 { 12862306a36Sopenharmony_ci compatible = "qcom,geni-se-qup"; 12962306a36Sopenharmony_ci reg = <0 0x008c0000 0 0x6000>; 13062306a36Sopenharmony_ci clock-names = "m-ahb", "s-ahb"; 13162306a36Sopenharmony_ci clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 13262306a36Sopenharmony_ci <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 13362306a36Sopenharmony_ci #address-cells = <2>; 13462306a36Sopenharmony_ci #size-cells = <2>; 13562306a36Sopenharmony_ci ranges; 13662306a36Sopenharmony_ci 13762306a36Sopenharmony_ci i2c0: i2c@a94000 { 13862306a36Sopenharmony_ci compatible = "qcom,geni-i2c"; 13962306a36Sopenharmony_ci reg = <0 0xa94000 0 0x4000>; 14062306a36Sopenharmony_ci interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 14162306a36Sopenharmony_ci clock-names = "se"; 14262306a36Sopenharmony_ci clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 14362306a36Sopenharmony_ci pinctrl-names = "default", "sleep"; 14462306a36Sopenharmony_ci pinctrl-0 = <&qup_1_i2c_5_active>; 14562306a36Sopenharmony_ci pinctrl-1 = <&qup_1_i2c_5_sleep>; 14662306a36Sopenharmony_ci #address-cells = <1>; 14762306a36Sopenharmony_ci #size-cells = <0>; 14862306a36Sopenharmony_ci }; 14962306a36Sopenharmony_ci 15062306a36Sopenharmony_ci uart0: serial@a88000 { 15162306a36Sopenharmony_ci compatible = "qcom,geni-uart"; 15262306a36Sopenharmony_ci reg = <0 0xa88000 0 0x7000>; 15362306a36Sopenharmony_ci interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 15462306a36Sopenharmony_ci clock-names = "se"; 15562306a36Sopenharmony_ci clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 15662306a36Sopenharmony_ci pinctrl-names = "default", "sleep"; 15762306a36Sopenharmony_ci pinctrl-0 = <&qup_1_uart_3_active>; 15862306a36Sopenharmony_ci pinctrl-1 = <&qup_1_uart_3_sleep>; 15962306a36Sopenharmony_ci }; 16062306a36Sopenharmony_ci }; 16162306a36Sopenharmony_ci }; 16262306a36Sopenharmony_ci 16362306a36Sopenharmony_ci... 164