162306a36Sopenharmony_ciXilinx Zynq Reset Manager 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThe Zynq AP-SoC has several different resets. 462306a36Sopenharmony_ci 562306a36Sopenharmony_ciSee Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciRequired properties: 862306a36Sopenharmony_ci- compatible: "xlnx,zynq-reset" 962306a36Sopenharmony_ci- reg: SLCR offset and size taken via syscon <0x200 0x48> 1062306a36Sopenharmony_ci- syscon: <&slcr> 1162306a36Sopenharmony_ci This should be a phandle to the Zynq's SLCR registers. 1262306a36Sopenharmony_ci- #reset-cells: Must be 1 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciThe Zynq Reset Manager needs to be a childnode of the SLCR. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciExample: 1762306a36Sopenharmony_ci rstc: rstc@200 { 1862306a36Sopenharmony_ci compatible = "xlnx,zynq-reset"; 1962306a36Sopenharmony_ci reg = <0x200 0x48>; 2062306a36Sopenharmony_ci #reset-cells = <1>; 2162306a36Sopenharmony_ci syscon = <&slcr>; 2262306a36Sopenharmony_ci }; 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciReset outputs: 2562306a36Sopenharmony_ci 0 : soft reset 2662306a36Sopenharmony_ci 32 : ddr reset 2762306a36Sopenharmony_ci 64 : topsw reset 2862306a36Sopenharmony_ci 96 : dmac reset 2962306a36Sopenharmony_ci 128: usb0 reset 3062306a36Sopenharmony_ci 129: usb1 reset 3162306a36Sopenharmony_ci 160: gem0 reset 3262306a36Sopenharmony_ci 161: gem1 reset 3362306a36Sopenharmony_ci 164: gem0 rx reset 3462306a36Sopenharmony_ci 165: gem1 rx reset 3562306a36Sopenharmony_ci 166: gem0 ref reset 3662306a36Sopenharmony_ci 167: gem1 ref reset 3762306a36Sopenharmony_ci 192: sdio0 reset 3862306a36Sopenharmony_ci 193: sdio1 reset 3962306a36Sopenharmony_ci 196: sdio0 ref reset 4062306a36Sopenharmony_ci 197: sdio1 ref reset 4162306a36Sopenharmony_ci 224: spi0 reset 4262306a36Sopenharmony_ci 225: spi1 reset 4362306a36Sopenharmony_ci 226: spi0 ref reset 4462306a36Sopenharmony_ci 227: spi1 ref reset 4562306a36Sopenharmony_ci 256: can0 reset 4662306a36Sopenharmony_ci 257: can1 reset 4762306a36Sopenharmony_ci 258: can0 ref reset 4862306a36Sopenharmony_ci 259: can1 ref reset 4962306a36Sopenharmony_ci 288: i2c0 reset 5062306a36Sopenharmony_ci 289: i2c1 reset 5162306a36Sopenharmony_ci 320: uart0 reset 5262306a36Sopenharmony_ci 321: uart1 reset 5362306a36Sopenharmony_ci 322: uart0 ref reset 5462306a36Sopenharmony_ci 323: uart1 ref reset 5562306a36Sopenharmony_ci 352: gpio reset 5662306a36Sopenharmony_ci 384: lqspi reset 5762306a36Sopenharmony_ci 385: qspi ref reset 5862306a36Sopenharmony_ci 416: smc reset 5962306a36Sopenharmony_ci 417: smc ref reset 6062306a36Sopenharmony_ci 448: ocm reset 6162306a36Sopenharmony_ci 512: fpga0 out reset 6262306a36Sopenharmony_ci 513: fpga1 out reset 6362306a36Sopenharmony_ci 514: fpga2 out reset 6462306a36Sopenharmony_ci 515: fpga3 out reset 6562306a36Sopenharmony_ci 544: a9 reset 0 6662306a36Sopenharmony_ci 545: a9 reset 1 6762306a36Sopenharmony_ci 552: peri reset 6862306a36Sopenharmony_ci 69