162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Renesas RZ/{G2L,V2L} USBPHY Control 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Biju Das <biju.das.jz@bp.renesas.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: 1362306a36Sopenharmony_ci The RZ/G2L USBPHY Control mainly controls reset and power down of the 1462306a36Sopenharmony_ci USB/PHY. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciproperties: 1762306a36Sopenharmony_ci compatible: 1862306a36Sopenharmony_ci items: 1962306a36Sopenharmony_ci - enum: 2062306a36Sopenharmony_ci - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL 2162306a36Sopenharmony_ci - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 2262306a36Sopenharmony_ci - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 2362306a36Sopenharmony_ci - const: renesas,rzg2l-usbphy-ctrl 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci reg: 2662306a36Sopenharmony_ci maxItems: 1 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci clocks: 2962306a36Sopenharmony_ci maxItems: 1 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci resets: 3262306a36Sopenharmony_ci maxItems: 1 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci power-domains: 3562306a36Sopenharmony_ci maxItems: 1 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci '#reset-cells': 3862306a36Sopenharmony_ci const: 1 3962306a36Sopenharmony_ci description: | 4062306a36Sopenharmony_ci The phandle's argument in the reset specifier is the PHY reset associated 4162306a36Sopenharmony_ci with the USB port. 4262306a36Sopenharmony_ci 0 = Port 1 Phy reset 4362306a36Sopenharmony_ci 1 = Port 2 Phy reset 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_cirequired: 4662306a36Sopenharmony_ci - compatible 4762306a36Sopenharmony_ci - reg 4862306a36Sopenharmony_ci - clocks 4962306a36Sopenharmony_ci - resets 5062306a36Sopenharmony_ci - power-domains 5162306a36Sopenharmony_ci - '#reset-cells' 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_ciadditionalProperties: false 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciexamples: 5662306a36Sopenharmony_ci - | 5762306a36Sopenharmony_ci #include <dt-bindings/clock/r9a07g044-cpg.h> 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci phyrst: usbphy-ctrl@11c40000 { 6062306a36Sopenharmony_ci compatible = "renesas,r9a07g044-usbphy-ctrl", 6162306a36Sopenharmony_ci "renesas,rzg2l-usbphy-ctrl"; 6262306a36Sopenharmony_ci reg = <0x11c40000 0x10000>; 6362306a36Sopenharmony_ci clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 6462306a36Sopenharmony_ci resets = <&cpg R9A07G044_USB_PRESETN>; 6562306a36Sopenharmony_ci power-domains = <&cpg>; 6662306a36Sopenharmony_ci #reset-cells = <1>; 6762306a36Sopenharmony_ci }; 68