162306a36Sopenharmony_ciNXP LPC1850 Reset Generation Unit (RGU) 262306a36Sopenharmony_ci======================================== 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciPlease also refer to reset.txt in this directory for common reset 562306a36Sopenharmony_cicontroller binding usage. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciRequired properties: 862306a36Sopenharmony_ci- compatible: Should be "nxp,lpc1850-rgu" 962306a36Sopenharmony_ci- reg: register base and length 1062306a36Sopenharmony_ci- clocks: phandle and clock specifier to RGU clocks 1162306a36Sopenharmony_ci- clock-names: should contain "delay" and "reg" 1262306a36Sopenharmony_ci- #reset-cells: should be 1 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciSee table below for valid peripheral reset numbers. Numbers not 1562306a36Sopenharmony_ciin the table below are either reserved or not applicable for 1662306a36Sopenharmony_cinormal operation. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciReset Peripheral 1962306a36Sopenharmony_ci 9 System control unit (SCU) 2062306a36Sopenharmony_ci 12 ARM Cortex-M0 subsystem core (LPC43xx only) 2162306a36Sopenharmony_ci 13 CPU core 2262306a36Sopenharmony_ci 16 LCD controller 2362306a36Sopenharmony_ci 17 USB0 2462306a36Sopenharmony_ci 18 USB1 2562306a36Sopenharmony_ci 19 DMA 2662306a36Sopenharmony_ci 20 SDIO 2762306a36Sopenharmony_ci 21 External memory controller (EMC) 2862306a36Sopenharmony_ci 22 Ethernet 2962306a36Sopenharmony_ci 25 Flash bank A 3062306a36Sopenharmony_ci 27 EEPROM 3162306a36Sopenharmony_ci 28 GPIO 3262306a36Sopenharmony_ci 29 Flash bank B 3362306a36Sopenharmony_ci 32 Timer0 3462306a36Sopenharmony_ci 33 Timer1 3562306a36Sopenharmony_ci 34 Timer2 3662306a36Sopenharmony_ci 35 Timer3 3762306a36Sopenharmony_ci 36 Repetitive Interrupt timer (RIT) 3862306a36Sopenharmony_ci 37 State Configurable Timer (SCT) 3962306a36Sopenharmony_ci 38 Motor control PWM (MCPWM) 4062306a36Sopenharmony_ci 39 QEI 4162306a36Sopenharmony_ci 40 ADC0 4262306a36Sopenharmony_ci 41 ADC1 4362306a36Sopenharmony_ci 42 DAC 4462306a36Sopenharmony_ci 44 USART0 4562306a36Sopenharmony_ci 45 UART1 4662306a36Sopenharmony_ci 46 USART2 4762306a36Sopenharmony_ci 47 USART3 4862306a36Sopenharmony_ci 48 I2C0 4962306a36Sopenharmony_ci 49 I2C1 5062306a36Sopenharmony_ci 50 SSP0 5162306a36Sopenharmony_ci 51 SSP1 5262306a36Sopenharmony_ci 52 I2S0 and I2S1 5362306a36Sopenharmony_ci 53 Serial Flash Interface (SPIFI) 5462306a36Sopenharmony_ci 54 C_CAN1 5562306a36Sopenharmony_ci 55 C_CAN0 5662306a36Sopenharmony_ci 56 ARM Cortex-M0 application core (LPC4370 only) 5762306a36Sopenharmony_ci 57 SGPIO (LPC43xx only) 5862306a36Sopenharmony_ci 58 SPI (LPC43xx only) 5962306a36Sopenharmony_ci 60 ADCHS (12-bit ADC) (LPC4370 only) 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ciRefer to NXP LPC18xx or LPC43xx user manual for more details about 6262306a36Sopenharmony_cithe reset signals and the connected block/peripheral. 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ciReset provider example: 6562306a36Sopenharmony_cirgu: reset-controller@40053000 { 6662306a36Sopenharmony_ci compatible = "nxp,lpc1850-rgu"; 6762306a36Sopenharmony_ci reg = <0x40053000 0x1000>; 6862306a36Sopenharmony_ci clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 6962306a36Sopenharmony_ci clock-names = "delay", "reg"; 7062306a36Sopenharmony_ci #reset-cells = <1>; 7162306a36Sopenharmony_ci}; 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ciReset consumer example: 7462306a36Sopenharmony_cimac: ethernet@40010000 { 7562306a36Sopenharmony_ci compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 7662306a36Sopenharmony_ci reg = <0x40010000 0x2000>; 7762306a36Sopenharmony_ci interrupts = <5>; 7862306a36Sopenharmony_ci interrupt-names = "macirq"; 7962306a36Sopenharmony_ci clocks = <&ccu1 CLK_CPU_ETHERNET>; 8062306a36Sopenharmony_ci clock-names = "stmmaceth"; 8162306a36Sopenharmony_ci resets = <&rgu 22>; 8262306a36Sopenharmony_ci reset-names = "stmmaceth"; 8362306a36Sopenharmony_ci}; 84