162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Xilinx R5F processor subsystem
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Ben Levinsky <ben.levinsky@amd.com>
1162306a36Sopenharmony_ci  - Tanmay Shah <tanmay.shah@amd.com>
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cidescription: |
1462306a36Sopenharmony_ci  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
1562306a36Sopenharmony_ci  real-time processing based on the Cortex-R5F processor core from ARM.
1662306a36Sopenharmony_ci  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
1762306a36Sopenharmony_ci  floating-point unit that implements the Arm VFPv3 instruction set.
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ciproperties:
2062306a36Sopenharmony_ci  compatible:
2162306a36Sopenharmony_ci    const: xlnx,zynqmp-r5fss
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_ci  xlnx,cluster-mode:
2462306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32
2562306a36Sopenharmony_ci    enum: [0, 1, 2]
2662306a36Sopenharmony_ci    description: |
2762306a36Sopenharmony_ci      The RPU MPCore can operate in split mode (Dual-processor performance), Safety
2862306a36Sopenharmony_ci      lock-step mode(Both RPU cores execute the same code in lock-step,
2962306a36Sopenharmony_ci      clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
3062306a36Sopenharmony_ci      core 1 runs normally). The processor does not support dynamic configuration.
3162306a36Sopenharmony_ci      Switching between modes is only permitted immediately after a processor reset.
3262306a36Sopenharmony_ci      If set to  1 then lockstep mode and if 0 then split mode.
3362306a36Sopenharmony_ci      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
3462306a36Sopenharmony_ci      In summary,
3562306a36Sopenharmony_ci      0: split mode
3662306a36Sopenharmony_ci      1: lockstep mode (default)
3762306a36Sopenharmony_ci      2: single cpu mode
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_cipatternProperties:
4062306a36Sopenharmony_ci  "^r5f-[a-f0-9]+$":
4162306a36Sopenharmony_ci    type: object
4262306a36Sopenharmony_ci    description: |
4362306a36Sopenharmony_ci      The RPU is located in the Low Power Domain of the Processor Subsystem.
4462306a36Sopenharmony_ci      Each processor includes separate L1 instruction and data caches and
4562306a36Sopenharmony_ci      tightly coupled memories (TCM). System memory is cacheable, but the TCM
4662306a36Sopenharmony_ci      memory space is non-cacheable.
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci      Each RPU contains one 64KB memory and two 32KB memories that
4962306a36Sopenharmony_ci      are accessed via the TCM A and B port interfaces, for a total of 128KB
5062306a36Sopenharmony_ci      per processor. In lock-step mode, the processor has access to 256KB of
5162306a36Sopenharmony_ci      TCM memory.
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci    properties:
5462306a36Sopenharmony_ci      compatible:
5562306a36Sopenharmony_ci        const: xlnx,zynqmp-r5f
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ci      power-domains:
5862306a36Sopenharmony_ci        maxItems: 1
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci      mboxes:
6162306a36Sopenharmony_ci        minItems: 1
6262306a36Sopenharmony_ci        items:
6362306a36Sopenharmony_ci          - description: mailbox channel to send data to RPU
6462306a36Sopenharmony_ci          - description: mailbox channel to receive data from RPU
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ci      mbox-names:
6762306a36Sopenharmony_ci        minItems: 1
6862306a36Sopenharmony_ci        items:
6962306a36Sopenharmony_ci          - const: tx
7062306a36Sopenharmony_ci          - const: rx
7162306a36Sopenharmony_ci
7262306a36Sopenharmony_ci      sram:
7362306a36Sopenharmony_ci        $ref: /schemas/types.yaml#/definitions/phandle-array
7462306a36Sopenharmony_ci        minItems: 1
7562306a36Sopenharmony_ci        maxItems: 8
7662306a36Sopenharmony_ci        items:
7762306a36Sopenharmony_ci          maxItems: 1
7862306a36Sopenharmony_ci        description: |
7962306a36Sopenharmony_ci          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
8062306a36Sopenharmony_ci          the RPU can execute instructions and access data from the OCM memory,
8162306a36Sopenharmony_ci          the main DDR memory, and other system memories.
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci          The regions should be defined as child nodes of the respective SRAM
8462306a36Sopenharmony_ci          node, and should be defined as per the generic bindings in
8562306a36Sopenharmony_ci          Documentation/devicetree/bindings/sram/sram.yaml
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_ci      memory-region:
8862306a36Sopenharmony_ci        description: |
8962306a36Sopenharmony_ci          List of phandles to the reserved memory regions associated with the
9062306a36Sopenharmony_ci          remoteproc device. This is variable and describes the memories shared with
9162306a36Sopenharmony_ci          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
9262306a36Sopenharmony_ci          vrings, ...). This reserved memory region will be allocated in DDR memory.
9362306a36Sopenharmony_ci        minItems: 1
9462306a36Sopenharmony_ci        maxItems: 8
9562306a36Sopenharmony_ci        items:
9662306a36Sopenharmony_ci          - description: region used for RPU firmware image section
9762306a36Sopenharmony_ci          - description: vdev buffer
9862306a36Sopenharmony_ci          - description: vring0
9962306a36Sopenharmony_ci          - description: vring1
10062306a36Sopenharmony_ci        additionalItems: true
10162306a36Sopenharmony_ci
10262306a36Sopenharmony_ci    required:
10362306a36Sopenharmony_ci      - compatible
10462306a36Sopenharmony_ci      - power-domains
10562306a36Sopenharmony_ci
10662306a36Sopenharmony_ci    unevaluatedProperties: false
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_cirequired:
10962306a36Sopenharmony_ci  - compatible
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ciadditionalProperties: false
11262306a36Sopenharmony_ci
11362306a36Sopenharmony_ciexamples:
11462306a36Sopenharmony_ci  - |
11562306a36Sopenharmony_ci    remoteproc {
11662306a36Sopenharmony_ci        compatible = "xlnx,zynqmp-r5fss";
11762306a36Sopenharmony_ci        xlnx,cluster-mode = <1>;
11862306a36Sopenharmony_ci
11962306a36Sopenharmony_ci        r5f-0 {
12062306a36Sopenharmony_ci            compatible = "xlnx,zynqmp-r5f";
12162306a36Sopenharmony_ci            power-domains = <&zynqmp_firmware 0x7>;
12262306a36Sopenharmony_ci            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
12362306a36Sopenharmony_ci            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
12462306a36Sopenharmony_ci            mbox-names = "tx", "rx";
12562306a36Sopenharmony_ci        };
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ci        r5f-1 {
12862306a36Sopenharmony_ci            compatible = "xlnx,zynqmp-r5f";
12962306a36Sopenharmony_ci            power-domains = <&zynqmp_firmware 0x8>;
13062306a36Sopenharmony_ci            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
13162306a36Sopenharmony_ci            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
13262306a36Sopenharmony_ci            mbox-names = "tx", "rx";
13362306a36Sopenharmony_ci        };
13462306a36Sopenharmony_ci    };
13562306a36Sopenharmony_ci...
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