162306a36Sopenharmony_ci* Freescale QorIQ 1588 timer based PTP clock
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciGeneral Properties:
462306a36Sopenharmony_ci
562306a36Sopenharmony_ci  - compatible   Should be "fsl,etsec-ptp" for eTSEC
662306a36Sopenharmony_ci                 Should be "fsl,fman-ptp-timer" for DPAA FMan
762306a36Sopenharmony_ci                 Should be "fsl,dpaa2-ptp" for DPAA2
862306a36Sopenharmony_ci                 Should be "fsl,enetc-ptp" for ENETC
962306a36Sopenharmony_ci  - reg          Offset and length of the register set for the device
1062306a36Sopenharmony_ci  - interrupts   There should be at least two interrupts. Some devices
1162306a36Sopenharmony_ci                 have as many as four PTP related interrupts.
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ciClock Properties:
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1562306a36Sopenharmony_ci  - fsl,cksel        Timer reference clock source.
1662306a36Sopenharmony_ci  - fsl,tclk-period  Timer reference clock period in nanoseconds.
1762306a36Sopenharmony_ci  - fsl,tmr-prsc     Prescaler, divides the output clock.
1862306a36Sopenharmony_ci  - fsl,tmr-add      Frequency compensation value.
1962306a36Sopenharmony_ci  - fsl,tmr-fiper1   Fixed interval period pulse generator.
2062306a36Sopenharmony_ci  - fsl,tmr-fiper2   Fixed interval period pulse generator.
2162306a36Sopenharmony_ci  - fsl,tmr-fiper3   Fixed interval period pulse generator.
2262306a36Sopenharmony_ci                     Supported only on DPAA2 and ENETC hardware.
2362306a36Sopenharmony_ci  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
2462306a36Sopenharmony_ci  - fsl,extts-fifo   The presence of this property indicates hardware
2562306a36Sopenharmony_ci		     support for the external trigger stamp FIFO.
2662306a36Sopenharmony_ci  - little-endian    The presence of this property indicates the 1588 timer
2762306a36Sopenharmony_ci		     IP block is little-endian mode. The default endian mode
2862306a36Sopenharmony_ci		     is big-endian.
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci  These properties set the operational parameters for the PTP
3162306a36Sopenharmony_ci  clock. You must choose these carefully for the clock to work right.
3262306a36Sopenharmony_ci  Here is how to figure good values:
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci  TimerOsc     = selected reference clock   MHz
3562306a36Sopenharmony_ci  tclk_period  = desired clock period       nanoseconds
3662306a36Sopenharmony_ci  NominalFreq  = 1000 / tclk_period         MHz
3762306a36Sopenharmony_ci  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
3862306a36Sopenharmony_ci  tmr_add      = ceil(2^32 / FreqDivRatio)
3962306a36Sopenharmony_ci  OutputClock  = NominalFreq / tmr_prsc     MHz
4062306a36Sopenharmony_ci  PulseWidth   = 1 / OutputClock            microseconds
4162306a36Sopenharmony_ci  FiperFreq1   = desired frequency in Hz
4262306a36Sopenharmony_ci  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
4362306a36Sopenharmony_ci  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
4462306a36Sopenharmony_ci  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
4762306a36Sopenharmony_ci  driver expects that tmr_fiper1 will be correctly set to produce a 1
4862306a36Sopenharmony_ci  Pulse Per Second (PPS) signal, since this will be offered to the PPS
4962306a36Sopenharmony_ci  subsystem to synchronize the Linux clock.
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_ci  Reference clock source is determined by the value, which is holded
5262306a36Sopenharmony_ci  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
5362306a36Sopenharmony_ci  value, which will be directly written in those bits, that is why,
5462306a36Sopenharmony_ci  according to reference manual, the next clock sources can be used:
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ci  For eTSEC,
5762306a36Sopenharmony_ci  <0> - external high precision timer reference clock (TSEC_TMR_CLK
5862306a36Sopenharmony_ci        input is used for this purpose);
5962306a36Sopenharmony_ci  <1> - eTSEC system clock;
6062306a36Sopenharmony_ci  <2> - eTSEC1 transmit clock;
6162306a36Sopenharmony_ci  <3> - RTC clock input.
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci  For DPAA FMan,
6462306a36Sopenharmony_ci  <0> - external high precision timer reference clock (TMR_1588_CLK)
6562306a36Sopenharmony_ci  <1> - MAC system clock (1/2 FMan clock)
6662306a36Sopenharmony_ci  <2> - reserved
6762306a36Sopenharmony_ci  <3> - RTC clock oscillator
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ci  When this attribute is not used, the IEEE 1588 timer reference clock
7062306a36Sopenharmony_ci  will use the eTSEC system clock (for Gianfar) or the MAC system
7162306a36Sopenharmony_ci  clock (for DPAA).
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7362306a36Sopenharmony_ciExample:
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7562306a36Sopenharmony_ci	ptp_clock@24e00 {
7662306a36Sopenharmony_ci		compatible = "fsl,etsec-ptp";
7762306a36Sopenharmony_ci		reg = <0x24E00 0xB0>;
7862306a36Sopenharmony_ci		interrupts = <12 0x8 13 0x8>;
7962306a36Sopenharmony_ci		interrupt-parent = < &ipic >;
8062306a36Sopenharmony_ci		fsl,cksel       = <1>;
8162306a36Sopenharmony_ci		fsl,tclk-period = <10>;
8262306a36Sopenharmony_ci		fsl,tmr-prsc    = <100>;
8362306a36Sopenharmony_ci		fsl,tmr-add     = <0x999999A4>;
8462306a36Sopenharmony_ci		fsl,tmr-fiper1  = <0x3B9AC9F6>;
8562306a36Sopenharmony_ci		fsl,tmr-fiper2  = <0x00018696>;
8662306a36Sopenharmony_ci		fsl,max-adj     = <659999998>;
8762306a36Sopenharmony_ci	};
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