162306a36Sopenharmony_ci* Freescale MPIC timers 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- compatible: "fsl,mpic-global-timer" 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci- reg : Contains two regions. The first is the main timer register bank 762306a36Sopenharmony_ci (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control 862306a36Sopenharmony_ci register (TCRx) for the group. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci- fsl,available-ranges: use <start count> style section to define which 1162306a36Sopenharmony_ci timer interrupts can be used. This property is optional; without this, 1262306a36Sopenharmony_ci all timers within the group can be used. 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci- interrupts: one interrupt per timer in the group, in order, starting 1562306a36Sopenharmony_ci with timer zero. If timer-available-ranges is present, only the 1662306a36Sopenharmony_ci interrupts that correspond to available timers shall be present. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciExample: 1962306a36Sopenharmony_ci /* Note that this requires #interrupt-cells to be 4 */ 2062306a36Sopenharmony_ci timer0: timer@41100 { 2162306a36Sopenharmony_ci compatible = "fsl,mpic-global-timer"; 2262306a36Sopenharmony_ci reg = <0x41100 0x100 0x41300 4>; 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci /* Another AMP partition is using timers 0 and 1 */ 2562306a36Sopenharmony_ci fsl,available-ranges = <2 2>; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci interrupts = <2 0 3 0 2862306a36Sopenharmony_ci 3 0 3 0>; 2962306a36Sopenharmony_ci }; 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci timer1: timer@42100 { 3262306a36Sopenharmony_ci compatible = "fsl,mpic-global-timer"; 3362306a36Sopenharmony_ci reg = <0x42100 0x100 0x42300 4>; 3462306a36Sopenharmony_ci interrupts = <4 0 3 0 3562306a36Sopenharmony_ci 5 0 3 0 3662306a36Sopenharmony_ci 6 0 3 0 3762306a36Sopenharmony_ci 7 0 3 0>; 3862306a36Sopenharmony_ci }; 39