162306a36Sopenharmony_ci* FSL MPIC Message Registers 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis binding specifies what properties must be available in the device tree 462306a36Sopenharmony_cirepresentation of the message register blocks found in some FSL MPIC 562306a36Sopenharmony_ciimplementations. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciRequired properties: 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci - compatible: Specifies the compatibility list for the message register 1062306a36Sopenharmony_ci block. The type shall be <string-list> and the value shall be of the form 1162306a36Sopenharmony_ci "fsl,mpic-v<version>-msgr", where <version> is the version number of 1262306a36Sopenharmony_ci the MPIC containing the message registers. 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci - reg: Specifies the base physical address(s) and size(s) of the 1562306a36Sopenharmony_ci message register block's addressable register space. The type shall be 1662306a36Sopenharmony_ci <prop-encoded-array>. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci - interrupts: Specifies a list of interrupt-specifiers which are available 1962306a36Sopenharmony_ci for receiving interrupts. Interrupt-specifier consists of two cells: first 2062306a36Sopenharmony_ci cell is interrupt-number and second cell is level-sense. The type shall be 2162306a36Sopenharmony_ci <prop-encoded-array>. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciOptional properties: 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci - mpic-msgr-receive-mask: Specifies what registers in the containing block 2662306a36Sopenharmony_ci are allowed to receive interrupts. The value is a bit mask where a set 2762306a36Sopenharmony_ci bit at bit 'n' indicates that message register 'n' can receive interrupts. 2862306a36Sopenharmony_ci Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall 2962306a36Sopenharmony_ci be <u32>. If not present, then all of the message registers in the block 3062306a36Sopenharmony_ci are available. 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ciAliases: 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci An alias should be created for every message register block. They are not 3562306a36Sopenharmony_ci required, though. However, a particular implementation of this binding 3662306a36Sopenharmony_ci may require aliases to be present. Aliases are of the form 3762306a36Sopenharmony_ci 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. 3862306a36Sopenharmony_ci Numbers shall start at 0. 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ciExample: 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci aliases { 4362306a36Sopenharmony_ci mpic-msgr-block0 = &mpic_msgr_block0; 4462306a36Sopenharmony_ci mpic-msgr-block1 = &mpic_msgr_block1; 4562306a36Sopenharmony_ci }; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci mpic_msgr_block0: mpic-msgr-block@41400 { 4862306a36Sopenharmony_ci compatible = "fsl,mpic-v3.1-msgr"; 4962306a36Sopenharmony_ci reg = <0x41400 0x200>; 5062306a36Sopenharmony_ci // Message registers 0 and 2 in this block can receive interrupts on 5162306a36Sopenharmony_ci // sources 0xb0 and 0xb2, respectively. 5262306a36Sopenharmony_ci interrupts = <0xb0 2 0xb2 2>; 5362306a36Sopenharmony_ci mpic-msgr-receive-mask = <0x5>; 5462306a36Sopenharmony_ci }; 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci mpic_msgr_block1: mpic-msgr-block@42400 { 5762306a36Sopenharmony_ci compatible = "fsl,mpic-v3.1-msgr"; 5862306a36Sopenharmony_ci reg = <0x42400 0x200>; 5962306a36Sopenharmony_ci // Message registers 0 and 2 in this block can receive interrupts on 6062306a36Sopenharmony_ci // sources 0xb4 and 0xb6, respectively. 6162306a36Sopenharmony_ci interrupts = <0xb4 2 0xb6 2>; 6262306a36Sopenharmony_ci mpic-msgr-receive-mask = <0x5>; 6362306a36Sopenharmony_ci }; 64