162306a36Sopenharmony_ci* Freescale DMA Controllers 262306a36Sopenharmony_ci 362306a36Sopenharmony_ci** Freescale Elo DMA Controller 462306a36Sopenharmony_ci This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx 562306a36Sopenharmony_ci series chips such as mpc8315, mpc8349, mpc8379 etc. 662306a36Sopenharmony_ci 762306a36Sopenharmony_ciRequired properties: 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci- compatible : must include "fsl,elo-dma" 1062306a36Sopenharmony_ci- reg : DMA General Status Register, i.e. DGSR which contains 1162306a36Sopenharmony_ci status for all the 4 DMA channels 1262306a36Sopenharmony_ci- ranges : describes the mapping between the address space of the 1362306a36Sopenharmony_ci DMA channels and the address space of the DMA controller 1462306a36Sopenharmony_ci- cell-index : controller index. 0 for controller @ 0x8100 1562306a36Sopenharmony_ci- interrupts : interrupt specifier for DMA IRQ 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ci- DMA channel nodes: 1862306a36Sopenharmony_ci - compatible : must include "fsl,elo-dma-channel" 1962306a36Sopenharmony_ci However, see note below. 2062306a36Sopenharmony_ci - reg : DMA channel specific registers 2162306a36Sopenharmony_ci - cell-index : DMA channel index starts at 0. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciOptional properties: 2462306a36Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 2562306a36Sopenharmony_ci (on 83xx this is expected to be identical to 2662306a36Sopenharmony_ci the interrupts property of the parent node) 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciExample: 2962306a36Sopenharmony_ci dma@82a8 { 3062306a36Sopenharmony_ci #address-cells = <1>; 3162306a36Sopenharmony_ci #size-cells = <1>; 3262306a36Sopenharmony_ci compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 3362306a36Sopenharmony_ci reg = <0x82a8 4>; 3462306a36Sopenharmony_ci ranges = <0 0x8100 0x1a4>; 3562306a36Sopenharmony_ci interrupt-parent = <&ipic>; 3662306a36Sopenharmony_ci interrupts = <71 8>; 3762306a36Sopenharmony_ci cell-index = <0>; 3862306a36Sopenharmony_ci dma-channel@0 { 3962306a36Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 4062306a36Sopenharmony_ci cell-index = <0>; 4162306a36Sopenharmony_ci reg = <0 0x80>; 4262306a36Sopenharmony_ci interrupt-parent = <&ipic>; 4362306a36Sopenharmony_ci interrupts = <71 8>; 4462306a36Sopenharmony_ci }; 4562306a36Sopenharmony_ci dma-channel@80 { 4662306a36Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 4762306a36Sopenharmony_ci cell-index = <1>; 4862306a36Sopenharmony_ci reg = <0x80 0x80>; 4962306a36Sopenharmony_ci interrupt-parent = <&ipic>; 5062306a36Sopenharmony_ci interrupts = <71 8>; 5162306a36Sopenharmony_ci }; 5262306a36Sopenharmony_ci dma-channel@100 { 5362306a36Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 5462306a36Sopenharmony_ci cell-index = <2>; 5562306a36Sopenharmony_ci reg = <0x100 0x80>; 5662306a36Sopenharmony_ci interrupt-parent = <&ipic>; 5762306a36Sopenharmony_ci interrupts = <71 8>; 5862306a36Sopenharmony_ci }; 5962306a36Sopenharmony_ci dma-channel@180 { 6062306a36Sopenharmony_ci compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 6162306a36Sopenharmony_ci cell-index = <3>; 6262306a36Sopenharmony_ci reg = <0x180 0x80>; 6362306a36Sopenharmony_ci interrupt-parent = <&ipic>; 6462306a36Sopenharmony_ci interrupts = <71 8>; 6562306a36Sopenharmony_ci }; 6662306a36Sopenharmony_ci }; 6762306a36Sopenharmony_ci 6862306a36Sopenharmony_ci** Freescale EloPlus DMA Controller 6962306a36Sopenharmony_ci This is a 4-channel DMA controller with extended addresses and chaining, 7062306a36Sopenharmony_ci mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as 7162306a36Sopenharmony_ci mpc8540, mpc8641 p4080, bsc9131 etc. 7262306a36Sopenharmony_ci 7362306a36Sopenharmony_ciRequired properties: 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci- compatible : must include "fsl,eloplus-dma" 7662306a36Sopenharmony_ci- reg : DMA General Status Register, i.e. DGSR which contains 7762306a36Sopenharmony_ci status for all the 4 DMA channels 7862306a36Sopenharmony_ci- cell-index : controller index. 0 for controller @ 0x21000, 7962306a36Sopenharmony_ci 1 for controller @ 0xc000 8062306a36Sopenharmony_ci- ranges : describes the mapping between the address space of the 8162306a36Sopenharmony_ci DMA channels and the address space of the DMA controller 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ci- DMA channel nodes: 8462306a36Sopenharmony_ci - compatible : must include "fsl,eloplus-dma-channel" 8562306a36Sopenharmony_ci However, see note below. 8662306a36Sopenharmony_ci - cell-index : DMA channel index starts at 0. 8762306a36Sopenharmony_ci - reg : DMA channel specific registers 8862306a36Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 8962306a36Sopenharmony_ci 9062306a36Sopenharmony_ciExample: 9162306a36Sopenharmony_ci dma@21300 { 9262306a36Sopenharmony_ci #address-cells = <1>; 9362306a36Sopenharmony_ci #size-cells = <1>; 9462306a36Sopenharmony_ci compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 9562306a36Sopenharmony_ci reg = <0x21300 4>; 9662306a36Sopenharmony_ci ranges = <0 0x21100 0x200>; 9762306a36Sopenharmony_ci cell-index = <0>; 9862306a36Sopenharmony_ci dma-channel@0 { 9962306a36Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 10062306a36Sopenharmony_ci reg = <0 0x80>; 10162306a36Sopenharmony_ci cell-index = <0>; 10262306a36Sopenharmony_ci interrupt-parent = <&mpic>; 10362306a36Sopenharmony_ci interrupts = <20 2>; 10462306a36Sopenharmony_ci }; 10562306a36Sopenharmony_ci dma-channel@80 { 10662306a36Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 10762306a36Sopenharmony_ci reg = <0x80 0x80>; 10862306a36Sopenharmony_ci cell-index = <1>; 10962306a36Sopenharmony_ci interrupt-parent = <&mpic>; 11062306a36Sopenharmony_ci interrupts = <21 2>; 11162306a36Sopenharmony_ci }; 11262306a36Sopenharmony_ci dma-channel@100 { 11362306a36Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 11462306a36Sopenharmony_ci reg = <0x100 0x80>; 11562306a36Sopenharmony_ci cell-index = <2>; 11662306a36Sopenharmony_ci interrupt-parent = <&mpic>; 11762306a36Sopenharmony_ci interrupts = <22 2>; 11862306a36Sopenharmony_ci }; 11962306a36Sopenharmony_ci dma-channel@180 { 12062306a36Sopenharmony_ci compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 12162306a36Sopenharmony_ci reg = <0x180 0x80>; 12262306a36Sopenharmony_ci cell-index = <3>; 12362306a36Sopenharmony_ci interrupt-parent = <&mpic>; 12462306a36Sopenharmony_ci interrupts = <23 2>; 12562306a36Sopenharmony_ci }; 12662306a36Sopenharmony_ci }; 12762306a36Sopenharmony_ci 12862306a36Sopenharmony_ci** Freescale Elo3 DMA Controller 12962306a36Sopenharmony_ci DMA controller which has same function as EloPlus except that Elo3 has 8 13062306a36Sopenharmony_ci channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx 13162306a36Sopenharmony_ci series chips, such as t1040, t4240, b4860. 13262306a36Sopenharmony_ci 13362306a36Sopenharmony_ciRequired properties: 13462306a36Sopenharmony_ci 13562306a36Sopenharmony_ci- compatible : must include "fsl,elo3-dma" 13662306a36Sopenharmony_ci- reg : contains two entries for DMA General Status Registers, 13762306a36Sopenharmony_ci i.e. DGSR0 which includes status for channel 1~4, and 13862306a36Sopenharmony_ci DGSR1 for channel 5~8 13962306a36Sopenharmony_ci- ranges : describes the mapping between the address space of the 14062306a36Sopenharmony_ci DMA channels and the address space of the DMA controller 14162306a36Sopenharmony_ci 14262306a36Sopenharmony_ci- DMA channel nodes: 14362306a36Sopenharmony_ci - compatible : must include "fsl,eloplus-dma-channel" 14462306a36Sopenharmony_ci - reg : DMA channel specific registers 14562306a36Sopenharmony_ci - interrupts : interrupt specifier for DMA channel IRQ 14662306a36Sopenharmony_ci 14762306a36Sopenharmony_ciExample: 14862306a36Sopenharmony_cidma@100300 { 14962306a36Sopenharmony_ci #address-cells = <1>; 15062306a36Sopenharmony_ci #size-cells = <1>; 15162306a36Sopenharmony_ci compatible = "fsl,elo3-dma"; 15262306a36Sopenharmony_ci reg = <0x100300 0x4>, 15362306a36Sopenharmony_ci <0x100600 0x4>; 15462306a36Sopenharmony_ci ranges = <0x0 0x100100 0x500>; 15562306a36Sopenharmony_ci dma-channel@0 { 15662306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 15762306a36Sopenharmony_ci reg = <0x0 0x80>; 15862306a36Sopenharmony_ci interrupts = <28 2 0 0>; 15962306a36Sopenharmony_ci }; 16062306a36Sopenharmony_ci dma-channel@80 { 16162306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 16262306a36Sopenharmony_ci reg = <0x80 0x80>; 16362306a36Sopenharmony_ci interrupts = <29 2 0 0>; 16462306a36Sopenharmony_ci }; 16562306a36Sopenharmony_ci dma-channel@100 { 16662306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 16762306a36Sopenharmony_ci reg = <0x100 0x80>; 16862306a36Sopenharmony_ci interrupts = <30 2 0 0>; 16962306a36Sopenharmony_ci }; 17062306a36Sopenharmony_ci dma-channel@180 { 17162306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 17262306a36Sopenharmony_ci reg = <0x180 0x80>; 17362306a36Sopenharmony_ci interrupts = <31 2 0 0>; 17462306a36Sopenharmony_ci }; 17562306a36Sopenharmony_ci dma-channel@300 { 17662306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 17762306a36Sopenharmony_ci reg = <0x300 0x80>; 17862306a36Sopenharmony_ci interrupts = <76 2 0 0>; 17962306a36Sopenharmony_ci }; 18062306a36Sopenharmony_ci dma-channel@380 { 18162306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 18262306a36Sopenharmony_ci reg = <0x380 0x80>; 18362306a36Sopenharmony_ci interrupts = <77 2 0 0>; 18462306a36Sopenharmony_ci }; 18562306a36Sopenharmony_ci dma-channel@400 { 18662306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 18762306a36Sopenharmony_ci reg = <0x400 0x80>; 18862306a36Sopenharmony_ci interrupts = <78 2 0 0>; 18962306a36Sopenharmony_ci }; 19062306a36Sopenharmony_ci dma-channel@480 { 19162306a36Sopenharmony_ci compatible = "fsl,eloplus-dma-channel"; 19262306a36Sopenharmony_ci reg = <0x480 0x80>; 19362306a36Sopenharmony_ci interrupts = <79 2 0 0>; 19462306a36Sopenharmony_ci }; 19562306a36Sopenharmony_ci}; 19662306a36Sopenharmony_ci 19762306a36Sopenharmony_ciNote on DMA channel compatible properties: The compatible property must say 19862306a36Sopenharmony_ci"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA 19962306a36Sopenharmony_cidriver (fsldma). Any DMA channel used by fsldma cannot be used by another 20062306a36Sopenharmony_ciDMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA 20162306a36Sopenharmony_cichannel that should be used for another driver should not use 20262306a36Sopenharmony_ci"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for 20362306a36Sopenharmony_ciexample, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt 20462306a36Sopenharmony_cifor more information. 205