162306a36Sopenharmony_ciPPC4xx Clock Power Management (CPM) node 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci - compatible : compatible list, currently only "ibm,cpm" 562306a36Sopenharmony_ci - dcr-access-method : "native" 662306a36Sopenharmony_ci - dcr-reg : < DCR register range > 762306a36Sopenharmony_ci 862306a36Sopenharmony_ciOptional properties: 962306a36Sopenharmony_ci - er-offset : All 4xx SoCs with a CPM controller have 1062306a36Sopenharmony_ci one of two different order for the CPM 1162306a36Sopenharmony_ci registers. Some have the CPM registers 1262306a36Sopenharmony_ci in the following order (ER,FR,SR). The 1362306a36Sopenharmony_ci others have them in the following order 1462306a36Sopenharmony_ci (SR,ER,FR). For the second case set 1562306a36Sopenharmony_ci er-offset = <1>. 1662306a36Sopenharmony_ci - unused-units : specifier consist of one cell. For each 1762306a36Sopenharmony_ci bit in the cell, the corresponding bit 1862306a36Sopenharmony_ci in CPM will be set to turn off unused 1962306a36Sopenharmony_ci devices. 2062306a36Sopenharmony_ci - idle-doze : specifier consist of one cell. For each 2162306a36Sopenharmony_ci bit in the cell, the corresponding bit 2262306a36Sopenharmony_ci in CPM will be set to turn off unused 2362306a36Sopenharmony_ci devices. This is usually just CPM[CPU]. 2462306a36Sopenharmony_ci - standby : specifier consist of one cell. For each 2562306a36Sopenharmony_ci bit in the cell, the corresponding bit 2662306a36Sopenharmony_ci in CPM will be set on standby and 2762306a36Sopenharmony_ci restored on resume. 2862306a36Sopenharmony_ci - suspend : specifier consist of one cell. For each 2962306a36Sopenharmony_ci bit in the cell, the corresponding bit 3062306a36Sopenharmony_ci in CPM will be set on suspend (mem) and 3162306a36Sopenharmony_ci restored on resume. Note, for standby 3262306a36Sopenharmony_ci and suspend the corresponding bits can 3362306a36Sopenharmony_ci be different or the same. Usually for 3462306a36Sopenharmony_ci standby only class 2 and 3 units are set. 3562306a36Sopenharmony_ci However, the interface does not care. 3662306a36Sopenharmony_ci If they are the same, the additional 3762306a36Sopenharmony_ci power saving will be seeing if support 3862306a36Sopenharmony_ci is available to put the DDR in self 3962306a36Sopenharmony_ci refresh mode and any additional power 4062306a36Sopenharmony_ci saving techniques for the specific SoC. 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ciExample: 4362306a36Sopenharmony_ci CPM0: cpm { 4462306a36Sopenharmony_ci compatible = "ibm,cpm"; 4562306a36Sopenharmony_ci dcr-access-method = "native"; 4662306a36Sopenharmony_ci dcr-reg = <0x160 0x003>; 4762306a36Sopenharmony_ci er-offset = <0>; 4862306a36Sopenharmony_ci unused-units = <0x00000100>; 4962306a36Sopenharmony_ci idle-doze = <0x02000000>; 5062306a36Sopenharmony_ci standby = <0xfeff0000>; 5162306a36Sopenharmony_ci suspend = <0xfeff791d>; 5262306a36Sopenharmony_ci}; 53