162306a36Sopenharmony_ci* Device tree bindings for Texas Instruments keystone reset 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThis node is intended to allow SoC reset in case of software reset 462306a36Sopenharmony_ciof selected watchdogs. 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciThe Keystone SoCs can contain up to 4 watchdog timers to reset 762306a36Sopenharmony_ciSoC. Each watchdog timer event input is connected to the Reset Mux 862306a36Sopenharmony_ciblock. The Reset Mux block can be configured to cause reset or not. 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ciAdditionally soft or hard reset can be configured. 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciRequired properties: 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci- compatible: ti,keystone-reset 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to 1762306a36Sopenharmony_ci access pll controller registers and the offset to use 1862306a36Sopenharmony_ci reset control registers. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to 2162306a36Sopenharmony_ci access device state control registers and the offset 2262306a36Sopenharmony_ci in order to use mux block registers for all watchdogs. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciOptional properties: 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci- ti,soft-reset: Boolean option indicating soft reset. 2762306a36Sopenharmony_ci By default hard reset is used. 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci- ti,wdt-list: WDT list that can cause SoC reset. It's not related 3062306a36Sopenharmony_ci to WDT driver, it's just needed to enable a SoC related 3162306a36Sopenharmony_ci reset that's triggered by one of WDTs. The list is 3262306a36Sopenharmony_ci in format: <0>, <2>; It can be in random order and 3362306a36Sopenharmony_ci begins from 0 to 3, as keystone can contain up to 4 SoC 3462306a36Sopenharmony_ci reset watchdogs and can be in random order. 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ciExample 1: 3762306a36Sopenharmony_ciSetup keystone reset so that in case software reset or 3862306a36Sopenharmony_ciWDT0 is triggered it issues hard reset for SoC. 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_cipllctrl: pll-controller@2310000 { 4162306a36Sopenharmony_ci compatible = "ti,keystone-pllctrl", "syscon"; 4262306a36Sopenharmony_ci reg = <0x02310000 0x200>; 4362306a36Sopenharmony_ci}; 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_cidevctrl: device-state-control@2620000 { 4662306a36Sopenharmony_ci compatible = "ti,keystone-devctrl", "syscon"; 4762306a36Sopenharmony_ci reg = <0x02620000 0x1000>; 4862306a36Sopenharmony_ci}; 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_cirstctrl: reset-controller { 5162306a36Sopenharmony_ci compatible = "ti,keystone-reset"; 5262306a36Sopenharmony_ci ti,syscon-pll = <&pllctrl 0xe4>; 5362306a36Sopenharmony_ci ti,syscon-dev = <&devctrl 0x328>; 5462306a36Sopenharmony_ci ti,wdt-list = <0>; 5562306a36Sopenharmony_ci}; 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciExample 2: 5862306a36Sopenharmony_ciSetup keystone reset so that in case of software reset or 5962306a36Sopenharmony_ciWDT0 or WDT2 is triggered it issues soft reset for SoC. 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_cirstctrl: reset-controller { 6262306a36Sopenharmony_ci compatible = "ti,keystone-reset"; 6362306a36Sopenharmony_ci ti,syscon-pll = <&pllctrl 0xe4>; 6462306a36Sopenharmony_ci ti,syscon-dev = <&devctrl 0x328>; 6562306a36Sopenharmony_ci ti,wdt-list = <0>, <2>; 6662306a36Sopenharmony_ci ti,soft-reset; 6762306a36Sopenharmony_ci}; 68