162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: StarFive JH7110 AON Pin Controller
862306a36Sopenharmony_ci
962306a36Sopenharmony_cidescription: |
1062306a36Sopenharmony_ci  Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci  Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
1362306a36Sopenharmony_ci  can be multiplexed and have configurable bias, drive strength,
1462306a36Sopenharmony_ci  schmitt trigger etc.
1562306a36Sopenharmony_ci  Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_cimaintainers:
1862306a36Sopenharmony_ci  - Jianlong Huang <jianlong.huang@starfivetech.com>
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ciproperties:
2162306a36Sopenharmony_ci  compatible:
2262306a36Sopenharmony_ci    const: starfive,jh7110-aon-pinctrl
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci  reg:
2562306a36Sopenharmony_ci    maxItems: 1
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci  resets:
2862306a36Sopenharmony_ci    maxItems: 1
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci  interrupts:
3162306a36Sopenharmony_ci    maxItems: 1
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci  interrupt-controller: true
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci  '#interrupt-cells':
3662306a36Sopenharmony_ci    const: 2
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci  gpio-controller: true
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci  '#gpio-cells':
4162306a36Sopenharmony_ci    const: 2
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_cipatternProperties:
4462306a36Sopenharmony_ci  '-[0-9]+$':
4562306a36Sopenharmony_ci    type: object
4662306a36Sopenharmony_ci    additionalProperties: false
4762306a36Sopenharmony_ci    patternProperties:
4862306a36Sopenharmony_ci      '-pins$':
4962306a36Sopenharmony_ci        type: object
5062306a36Sopenharmony_ci        description: |
5162306a36Sopenharmony_ci          A pinctrl node should contain at least one subnode representing the
5262306a36Sopenharmony_ci          pinctrl groups available on the machine. Each subnode will list the
5362306a36Sopenharmony_ci          pins it needs, and how they should be configured, with regard to
5462306a36Sopenharmony_ci          muxer configuration, bias, input enable/disable, input schmitt
5562306a36Sopenharmony_ci          trigger enable/disable, slew-rate and drive strength.
5662306a36Sopenharmony_ci        allOf:
5762306a36Sopenharmony_ci          - $ref: /schemas/pinctrl/pincfg-node.yaml
5862306a36Sopenharmony_ci          - $ref: /schemas/pinctrl/pinmux-node.yaml
5962306a36Sopenharmony_ci        additionalProperties: false
6062306a36Sopenharmony_ci
6162306a36Sopenharmony_ci        properties:
6262306a36Sopenharmony_ci          pinmux:
6362306a36Sopenharmony_ci            description: |
6462306a36Sopenharmony_ci              The list of GPIOs and their mux settings that properties in the
6562306a36Sopenharmony_ci              node apply to. This should be set using the GPIOMUX macro.
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci          bias-disable: true
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ci          bias-pull-up:
7062306a36Sopenharmony_ci            type: boolean
7162306a36Sopenharmony_ci
7262306a36Sopenharmony_ci          bias-pull-down:
7362306a36Sopenharmony_ci            type: boolean
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci          drive-strength:
7662306a36Sopenharmony_ci            enum: [ 2, 4, 8, 12 ]
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci          input-enable: true
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci          input-disable: true
8162306a36Sopenharmony_ci
8262306a36Sopenharmony_ci          input-schmitt-enable: true
8362306a36Sopenharmony_ci
8462306a36Sopenharmony_ci          input-schmitt-disable: true
8562306a36Sopenharmony_ci
8662306a36Sopenharmony_ci          slew-rate:
8762306a36Sopenharmony_ci            maximum: 1
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_cirequired:
9062306a36Sopenharmony_ci  - compatible
9162306a36Sopenharmony_ci  - reg
9262306a36Sopenharmony_ci  - interrupts
9362306a36Sopenharmony_ci  - interrupt-controller
9462306a36Sopenharmony_ci  - '#interrupt-cells'
9562306a36Sopenharmony_ci  - gpio-controller
9662306a36Sopenharmony_ci  - '#gpio-cells'
9762306a36Sopenharmony_ci
9862306a36Sopenharmony_ciadditionalProperties: false
9962306a36Sopenharmony_ci
10062306a36Sopenharmony_ciexamples:
10162306a36Sopenharmony_ci  - |
10262306a36Sopenharmony_ci    pinctrl@17020000 {
10362306a36Sopenharmony_ci        compatible = "starfive,jh7110-aon-pinctrl";
10462306a36Sopenharmony_ci        reg = <0x17020000 0x10000>;
10562306a36Sopenharmony_ci        resets = <&aoncrg 2>;
10662306a36Sopenharmony_ci        interrupts = <85>;
10762306a36Sopenharmony_ci        interrupt-controller;
10862306a36Sopenharmony_ci        #interrupt-cells = <2>;
10962306a36Sopenharmony_ci        gpio-controller;
11062306a36Sopenharmony_ci        #gpio-cells = <2>;
11162306a36Sopenharmony_ci
11262306a36Sopenharmony_ci        pwm-0 {
11362306a36Sopenharmony_ci            pwm-pins {
11462306a36Sopenharmony_ci                pinmux = <0xff030802>;
11562306a36Sopenharmony_ci                bias-disable;
11662306a36Sopenharmony_ci                drive-strength = <12>;
11762306a36Sopenharmony_ci                input-disable;
11862306a36Sopenharmony_ci                input-schmitt-disable;
11962306a36Sopenharmony_ci                slew-rate = <0>;
12062306a36Sopenharmony_ci            };
12162306a36Sopenharmony_ci        };
12262306a36Sopenharmony_ci    };
12362306a36Sopenharmony_ci
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