162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Krzysztof Kozlowski <krzk@kernel.org> 1162306a36Sopenharmony_ci - Sylwester Nawrocki <s.nawrocki@samsung.com> 1262306a36Sopenharmony_ci - Tomasz Figa <tomasz.figa@gmail.com> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_cidescription: | 1562306a36Sopenharmony_ci This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 1662306a36Sopenharmony_ci controller. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for 2162306a36Sopenharmony_ci additional information and example. 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ciproperties: 2462306a36Sopenharmony_ci '#gpio-cells': 2562306a36Sopenharmony_ci const: 2 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci gpio-controller: true 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci '#interrupt-cells': 3062306a36Sopenharmony_ci description: 3162306a36Sopenharmony_ci For GPIO banks supporting external GPIO interrupts or external wake-up 3262306a36Sopenharmony_ci interrupts. 3362306a36Sopenharmony_ci const: 2 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci interrupt-controller: 3662306a36Sopenharmony_ci description: 3762306a36Sopenharmony_ci For GPIO banks supporting external GPIO interrupts or external wake-up 3862306a36Sopenharmony_ci interrupts. 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci interrupts: 4162306a36Sopenharmony_ci description: 4262306a36Sopenharmony_ci For GPIO banks supporting direct external wake-up interrupts (without 4362306a36Sopenharmony_ci multiplexing). Number of interrupts must match number of wake-up capable 4462306a36Sopenharmony_ci pins of this bank. 4562306a36Sopenharmony_ci minItems: 1 4662306a36Sopenharmony_ci maxItems: 8 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_cirequired: 4962306a36Sopenharmony_ci - '#gpio-cells' 5062306a36Sopenharmony_ci - gpio-controller 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ciadditionalProperties: false 53