162306a36Sopenharmony_ciQualcomm Atheros IPQ4019 TLMM block
262306a36Sopenharmony_ci
362306a36Sopenharmony_ciThis is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
462306a36Sopenharmony_ciplatform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
562306a36Sopenharmony_ci
662306a36Sopenharmony_ciRequired properties:
762306a36Sopenharmony_ci- compatible: "qcom,ipq4019-pinctrl"
862306a36Sopenharmony_ci- reg: Should be the base address and length of the TLMM block.
962306a36Sopenharmony_ci- interrupts: Should be the parent IRQ of the TLMM block.
1062306a36Sopenharmony_ci- interrupt-controller: Marks the device node as an interrupt controller.
1162306a36Sopenharmony_ci- #interrupt-cells: Should be two.
1262306a36Sopenharmony_ci- gpio-controller: Marks the device node as a GPIO controller.
1362306a36Sopenharmony_ci- #gpio-cells : Should be two.
1462306a36Sopenharmony_ci                The first cell is the gpio pin number and the
1562306a36Sopenharmony_ci                second cell is used for optional parameters.
1662306a36Sopenharmony_ci- gpio-ranges: see ../gpio/gpio.txt
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ciOptional properties:
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci- gpio-reserved-ranges: see ../gpio/gpio.txt
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ciPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
2362306a36Sopenharmony_cia general description of GPIO and interrupt bindings.
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ciPlease refer to pinctrl-bindings.txt in this directory for details of the
2662306a36Sopenharmony_cicommon pinctrl bindings used by client devices, including the meaning of the
2762306a36Sopenharmony_ciphrase "pin configuration node".
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ciThe pin configuration nodes act as a container for an arbitrary number of
3062306a36Sopenharmony_cisubnodes. Each of these subnodes represents some desired configuration for a
3162306a36Sopenharmony_cipin, a group, or a list of pins or groups. This configuration can include the
3262306a36Sopenharmony_cimux function to select on those pin(s)/group(s), and various pin configuration
3362306a36Sopenharmony_ciparameters, such as pull-up, drive strength, etc.
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ciThe name of each subnode is not important; all subnodes should be enumerated
3662306a36Sopenharmony_ciand processed purely based on their content.
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ciEach subnode only affects those parameters that are explicitly listed. In
3962306a36Sopenharmony_ciother words, a subnode that lists a mux function but no pin configuration
4062306a36Sopenharmony_ciparameters implies no information about any pin configuration parameters.
4162306a36Sopenharmony_ciSimilarly, a pin subnode that describes a pullup parameter implies no
4262306a36Sopenharmony_ciinformation about e.g. the mux function.
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ciThe following generic properties as defined in pinctrl-bindings.txt are valid
4662306a36Sopenharmony_cito specify in a pin configuration subnode:
4762306a36Sopenharmony_ci pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
4862306a36Sopenharmony_ci drive-strength.
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ciNon-empty subnodes must specify the 'pins' property.
5162306a36Sopenharmony_ciNote that not all properties are valid for all pins.
5262306a36Sopenharmony_ci
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ciValid values for qcom,pins are:
5562306a36Sopenharmony_ci  gpio0-gpio99
5662306a36Sopenharmony_ci    Supports mux, bias and drive-strength
5762306a36Sopenharmony_ci
5862306a36Sopenharmony_ciValid values for qcom,function are:
5962306a36Sopenharmony_ciaud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
6062306a36Sopenharmony_ciblsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
6162306a36Sopenharmony_cijtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
6262306a36Sopenharmony_cimdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
6362306a36Sopenharmony_cismart2, smart3, tm, wifi0, wifi1
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ciExample:
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci	tlmm: pinctrl@1000000 {
6862306a36Sopenharmony_ci		compatible = "qcom,ipq4019-pinctrl";
6962306a36Sopenharmony_ci		reg = <0x1000000 0x300000>;
7062306a36Sopenharmony_ci
7162306a36Sopenharmony_ci		gpio-controller;
7262306a36Sopenharmony_ci		#gpio-cells = <2>;
7362306a36Sopenharmony_ci		gpio-ranges = <&tlmm 0 0 100>;
7462306a36Sopenharmony_ci		interrupt-controller;
7562306a36Sopenharmony_ci		#interrupt-cells = <2>;
7662306a36Sopenharmony_ci		interrupts = <0 208 0>;
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci		serial_pins: serial_pinmux {
7962306a36Sopenharmony_ci			mux {
8062306a36Sopenharmony_ci				pins = "gpio60", "gpio61";
8162306a36Sopenharmony_ci				function = "blsp_uart0";
8262306a36Sopenharmony_ci				bias-disable;
8362306a36Sopenharmony_ci			};
8462306a36Sopenharmony_ci		};
8562306a36Sopenharmony_ci	};
86