162306a36Sopenharmony_ciMicrochip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
262306a36Sopenharmony_ci8-/16-bit I/O expander with serial interface (I2C/SPI)
362306a36Sopenharmony_ci
462306a36Sopenharmony_ciRequired properties:
562306a36Sopenharmony_ci- compatible : Should be
662306a36Sopenharmony_ci    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
762306a36Sopenharmony_ci    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
862306a36Sopenharmony_ci    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
962306a36Sopenharmony_ci    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci    - "microchip,mcp23s08" for  8 GPIO SPI version
1262306a36Sopenharmony_ci    - "microchip,mcp23s17" for 16 GPIO SPI version
1362306a36Sopenharmony_ci    - "microchip,mcp23s18" for 16 GPIO SPI version
1462306a36Sopenharmony_ci    - "microchip,mcp23008" for  8 GPIO I2C version or
1562306a36Sopenharmony_ci    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
1662306a36Sopenharmony_ci    - "microchip,mcp23018" for 16 GPIO I2C version
1762306a36Sopenharmony_ci    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
1862306a36Sopenharmony_ci    removed.
1962306a36Sopenharmony_ci- #gpio-cells : Should be two.
2062306a36Sopenharmony_ci  - first cell is the pin number
2162306a36Sopenharmony_ci  - second cell is used to specify flags as described in
2262306a36Sopenharmony_ci    'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
2362306a36Sopenharmony_ci    'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
2462306a36Sopenharmony_ci- gpio-controller : Marks the device node as a GPIO controller.
2562306a36Sopenharmony_ci- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
2662306a36Sopenharmony_ci        SPI uses this to specify the chipselect line which the chip is
2762306a36Sopenharmony_ci        connected to. The driver and the SPI variant of the chip support
2862306a36Sopenharmony_ci        multiple chips on the same chipselect. Have a look at
2962306a36Sopenharmony_ci        microchip,spi-present-mask below.
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ciRequired device specific properties (only for SPI chips):
3262306a36Sopenharmony_ci- mcp,spi-present-mask (DEPRECATED)
3362306a36Sopenharmony_ci- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
3462306a36Sopenharmony_ci        chips - as the name suggests. Multiple SPI chips can share the same
3562306a36Sopenharmony_ci        SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
3662306a36Sopenharmony_ci        chip connected with the corresponding spi address set. For example if
3762306a36Sopenharmony_ci        you have a chip with address 3 connected, you have to set bit3 to 1,
3862306a36Sopenharmony_ci        which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
3962306a36Sopenharmony_ci        possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
4062306a36Sopenharmony_ci        least one bit to 1 for SPI chips.
4162306a36Sopenharmony_ci    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
4262306a36Sopenharmony_ci    removed.
4362306a36Sopenharmony_ci- spi-max-frequency = The maximum frequency this chip is able to handle
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ciOptional properties:
4662306a36Sopenharmony_ci- #interrupt-cells : Should be two.
4762306a36Sopenharmony_ci  - first cell is the pin number
4862306a36Sopenharmony_ci  - second cell is used to specify flags.
4962306a36Sopenharmony_ci- interrupt-controller: Marks the device node as a interrupt controller.
5062306a36Sopenharmony_ci- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
5162306a36Sopenharmony_ci        the IRQ output as open drain active low.
5262306a36Sopenharmony_ci- reset-gpios: Corresponds to the active-low RESET# pin for the chip
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ciOptional device specific properties:
5562306a36Sopenharmony_ci- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
5662306a36Sopenharmony_ci        with two interrupt outputs (these are the devices ending with 17 and
5762306a36Sopenharmony_ci        those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
5862306a36Sopenharmony_ci        IO 8-15 are bank 2. These chips have two different interrupt outputs:
5962306a36Sopenharmony_ci        One for bank 1 and another for bank 2. If irq-mirror is set, both
6062306a36Sopenharmony_ci        interrupts are generated regardless of the bank that an input change
6162306a36Sopenharmony_ci        occurred on. If it is not set, the interrupt are only generated for the
6262306a36Sopenharmony_ci        bank they belong to.
6362306a36Sopenharmony_ci        On devices with only one interrupt output this property is useless.
6462306a36Sopenharmony_ci- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
6562306a36Sopenharmony_ci        configures the IRQ output polarity as active high.
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ciExample I2C (with interrupt):
6862306a36Sopenharmony_cigpiom1: gpio@20 {
6962306a36Sopenharmony_ci        compatible = "microchip,mcp23017";
7062306a36Sopenharmony_ci        gpio-controller;
7162306a36Sopenharmony_ci        #gpio-cells = <2>;
7262306a36Sopenharmony_ci        reg = <0x20>;
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ci        interrupt-parent = <&gpio1>;
7562306a36Sopenharmony_ci        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
7662306a36Sopenharmony_ci        interrupt-controller;
7762306a36Sopenharmony_ci        #interrupt-cells=<2>;
7862306a36Sopenharmony_ci        microchip,irq-mirror;
7962306a36Sopenharmony_ci};
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ciExample SPI:
8262306a36Sopenharmony_cigpiom1: gpio@0 {
8362306a36Sopenharmony_ci        compatible = "microchip,mcp23s17";
8462306a36Sopenharmony_ci        gpio-controller;
8562306a36Sopenharmony_ci        #gpio-cells = <2>;
8662306a36Sopenharmony_ci        microchip,spi-present-mask = <0x01>;
8762306a36Sopenharmony_ci        reg = <0>;
8862306a36Sopenharmony_ci        spi-max-frequency = <1000000>;
8962306a36Sopenharmony_ci};
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_ciPull-up configuration
9262306a36Sopenharmony_ci=====================
9362306a36Sopenharmony_ci
9462306a36Sopenharmony_ciIf pins are used as output, they can also be configured with pull-ups. This is
9562306a36Sopenharmony_cidone with pinctrl.
9662306a36Sopenharmony_ci
9762306a36Sopenharmony_ciPlease refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
9862306a36Sopenharmony_cifor details of the common pinctrl bindings used by client devices,
9962306a36Sopenharmony_ciincluding the meaning of the phrase "pin configuration node".
10062306a36Sopenharmony_ci
10162306a36Sopenharmony_ciOptional Pinmux properties:
10262306a36Sopenharmony_ci--------------------------
10362306a36Sopenharmony_ciFollowing properties are required if default setting of pins are required
10462306a36Sopenharmony_ciat boot.
10562306a36Sopenharmony_ci- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
10662306a36Sopenharmony_ci- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
10762306a36Sopenharmony_ci		<pinctrl-bindings.txt>.
10862306a36Sopenharmony_ci
10962306a36Sopenharmony_ciThe pin configurations are defined as child of the pinctrl states node. Each
11062306a36Sopenharmony_cisub-node have following properties:
11162306a36Sopenharmony_ci
11262306a36Sopenharmony_ciRequired properties:
11362306a36Sopenharmony_ci------------------
11462306a36Sopenharmony_ci- pins: List of pins. Valid values of pins properties are:
11562306a36Sopenharmony_ci		      gpio0 ... gpio7 for the devices with 8 GPIO pins and
11662306a36Sopenharmony_ci		      gpio0 ... gpio15 for the devices with 16 GPIO pins.
11762306a36Sopenharmony_ci
11862306a36Sopenharmony_ciOptional properties:
11962306a36Sopenharmony_ci-------------------
12062306a36Sopenharmony_ciThe following optional property is defined in the pinmux DT binding document
12162306a36Sopenharmony_ci<pinctrl-bindings.txt>. Absence of this property will leave the configuration
12262306a36Sopenharmony_ciin its default state.
12362306a36Sopenharmony_ci	bias-pull-up
12462306a36Sopenharmony_ci
12562306a36Sopenharmony_ciExample with pinctrl to pull-up output pins:
12662306a36Sopenharmony_cigpio21: gpio@21 {
12762306a36Sopenharmony_ci	compatible = "microchip,mcp23017";
12862306a36Sopenharmony_ci	gpio-controller;
12962306a36Sopenharmony_ci	#gpio-cells = <0x2>;
13062306a36Sopenharmony_ci	reg = <0x21>;
13162306a36Sopenharmony_ci	interrupt-parent = <&socgpio>;
13262306a36Sopenharmony_ci	interrupts = <0x17 0x8>;
13362306a36Sopenharmony_ci	interrupt-names = "mcp23017@21 irq";
13462306a36Sopenharmony_ci	interrupt-controller;
13562306a36Sopenharmony_ci	#interrupt-cells = <0x2>;
13662306a36Sopenharmony_ci	microchip,irq-mirror;
13762306a36Sopenharmony_ci	pinctrl-names = "default";
13862306a36Sopenharmony_ci	pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
13962306a36Sopenharmony_ci	reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
14062306a36Sopenharmony_ci
14162306a36Sopenharmony_ci	gpio21pullups: pinmux {
14262306a36Sopenharmony_ci		pins =	"gpio0", "gpio1", "gpio2", "gpio3",
14362306a36Sopenharmony_ci			"gpio4", "gpio5", "gpio6", "gpio7",
14462306a36Sopenharmony_ci			"gpio8", "gpio9", "gpio10", "gpio11",
14562306a36Sopenharmony_ci			"gpio12", "gpio13", "gpio14", "gpio15";
14662306a36Sopenharmony_ci		bias-pull-up;
14762306a36Sopenharmony_ci	};
14862306a36Sopenharmony_ci};
149