162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: MediaTek MT6795 Pin Controller
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
1162306a36Sopenharmony_ci  - Sean Wang <sean.wang@kernel.org>
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cidescription:
1462306a36Sopenharmony_ci  The MediaTek's MT6795 Pin controller is used to control SoC pins.
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ciproperties:
1762306a36Sopenharmony_ci  compatible:
1862306a36Sopenharmony_ci    const: mediatek,mt6795-pinctrl
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci  gpio-controller: true
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci  '#gpio-cells':
2362306a36Sopenharmony_ci    description:
2462306a36Sopenharmony_ci      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
2562306a36Sopenharmony_ci      the amount of cells must be specified as 2. See the below mentioned gpio
2662306a36Sopenharmony_ci      binding representation for description of particular cells.
2762306a36Sopenharmony_ci    const: 2
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_ci  gpio-ranges:
3062306a36Sopenharmony_ci    description: GPIO valid number range.
3162306a36Sopenharmony_ci    maxItems: 1
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci  reg:
3462306a36Sopenharmony_ci    description:
3562306a36Sopenharmony_ci      Physical address base for GPIO base and eint registers.
3662306a36Sopenharmony_ci    minItems: 2
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci  reg-names:
3962306a36Sopenharmony_ci    items:
4062306a36Sopenharmony_ci      - const: base
4162306a36Sopenharmony_ci      - const: eint
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci  interrupt-controller: true
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci  '#interrupt-cells':
4662306a36Sopenharmony_ci    const: 2
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci  interrupts:
4962306a36Sopenharmony_ci    description: Interrupt outputs to the system interrupt controller (sysirq).
5062306a36Sopenharmony_ci    minItems: 1
5162306a36Sopenharmony_ci    items:
5262306a36Sopenharmony_ci      - description: EINT interrupt
5362306a36Sopenharmony_ci      - description: EINT event_b interrupt
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci# PIN CONFIGURATION NODES
5662306a36Sopenharmony_cipatternProperties:
5762306a36Sopenharmony_ci  '-pins$':
5862306a36Sopenharmony_ci    type: object
5962306a36Sopenharmony_ci    additionalProperties: false
6062306a36Sopenharmony_ci    patternProperties:
6162306a36Sopenharmony_ci      '^pins':
6262306a36Sopenharmony_ci        type: object
6362306a36Sopenharmony_ci        additionalProperties: false
6462306a36Sopenharmony_ci        description: |
6562306a36Sopenharmony_ci          A pinctrl node should contain at least one subnodes representing the
6662306a36Sopenharmony_ci          pinctrl groups available on the machine. Each subnode will list the
6762306a36Sopenharmony_ci          pins it needs, and how they should be configured, with regard to muxer
6862306a36Sopenharmony_ci          configuration, pullups, drive strength, input enable/disable and input
6962306a36Sopenharmony_ci          schmitt.
7062306a36Sopenharmony_ci          An example of using macro:
7162306a36Sopenharmony_ci          pincontroller {
7262306a36Sopenharmony_ci            /* GPIO0 set as multifunction GPIO0 */
7362306a36Sopenharmony_ci            gpio-pins {
7462306a36Sopenharmony_ci              pins {
7562306a36Sopenharmony_ci                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
7662306a36Sopenharmony_ci              }
7762306a36Sopenharmony_ci            };
7862306a36Sopenharmony_ci            /* GPIO45 set as multifunction SDA0 */
7962306a36Sopenharmony_ci            i2c0-pins {
8062306a36Sopenharmony_ci              pins {
8162306a36Sopenharmony_ci                pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
8262306a36Sopenharmony_ci              }
8362306a36Sopenharmony_ci            };
8462306a36Sopenharmony_ci          };
8562306a36Sopenharmony_ci        $ref: pinmux-node.yaml
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_ci        properties:
8862306a36Sopenharmony_ci          pinmux:
8962306a36Sopenharmony_ci            description:
9062306a36Sopenharmony_ci              Integer array, represents gpio pin number and mux setting.
9162306a36Sopenharmony_ci              Supported pin number and mux varies for different SoCs, and are
9262306a36Sopenharmony_ci              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
9362306a36Sopenharmony_ci
9462306a36Sopenharmony_ci          drive-strength:
9562306a36Sopenharmony_ci            enum: [2, 4, 6, 8, 10, 12, 14, 16]
9662306a36Sopenharmony_ci
9762306a36Sopenharmony_ci          bias-pull-down:
9862306a36Sopenharmony_ci            oneOf:
9962306a36Sopenharmony_ci              - type: boolean
10062306a36Sopenharmony_ci              - enum: [100, 101, 102, 103]
10162306a36Sopenharmony_ci                description: mt6795 pull down PUPD/R0/R1 type define value.
10262306a36Sopenharmony_ci            description:
10362306a36Sopenharmony_ci              For normal pull down type, it is not necessary to specify R1R0
10462306a36Sopenharmony_ci              values; When pull down type is PUPD/R0/R1, adding R1R0 defines
10562306a36Sopenharmony_ci              will set different resistance values.
10662306a36Sopenharmony_ci
10762306a36Sopenharmony_ci          bias-pull-up:
10862306a36Sopenharmony_ci            oneOf:
10962306a36Sopenharmony_ci              - type: boolean
11062306a36Sopenharmony_ci              - enum: [100, 101, 102, 103]
11162306a36Sopenharmony_ci                description: mt6795 pull up PUPD/R0/R1 type define value.
11262306a36Sopenharmony_ci            description:
11362306a36Sopenharmony_ci              For normal pull up type, it is not necessary to specify R1R0
11462306a36Sopenharmony_ci              values; When pull up type is PUPD/R0/R1, adding R1R0 defines will
11562306a36Sopenharmony_ci              set different resistance values.
11662306a36Sopenharmony_ci
11762306a36Sopenharmony_ci          bias-disable: true
11862306a36Sopenharmony_ci
11962306a36Sopenharmony_ci          output-high: true
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ci          output-low: true
12262306a36Sopenharmony_ci
12362306a36Sopenharmony_ci          input-enable: true
12462306a36Sopenharmony_ci
12562306a36Sopenharmony_ci          input-disable: true
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ci          input-schmitt-enable: true
12862306a36Sopenharmony_ci
12962306a36Sopenharmony_ci          input-schmitt-disable: true
13062306a36Sopenharmony_ci
13162306a36Sopenharmony_ci          mediatek,pull-up-adv:
13262306a36Sopenharmony_ci            description: |
13362306a36Sopenharmony_ci              Pull up settings for 2 pull resistors, R0 and R1. User can
13462306a36Sopenharmony_ci              configure those special pins. Valid arguments are described as
13562306a36Sopenharmony_ci              below:
13662306a36Sopenharmony_ci              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
13762306a36Sopenharmony_ci              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
13862306a36Sopenharmony_ci              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
13962306a36Sopenharmony_ci              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
14062306a36Sopenharmony_ci            $ref: /schemas/types.yaml#/definitions/uint32
14162306a36Sopenharmony_ci            enum: [0, 1, 2, 3]
14262306a36Sopenharmony_ci
14362306a36Sopenharmony_ci          mediatek,pull-down-adv:
14462306a36Sopenharmony_ci            description: |
14562306a36Sopenharmony_ci              Pull down settings for 2 pull resistors, R0 and R1. User can
14662306a36Sopenharmony_ci              configure those special pins. Valid arguments are described as
14762306a36Sopenharmony_ci              below:
14862306a36Sopenharmony_ci              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
14962306a36Sopenharmony_ci              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
15062306a36Sopenharmony_ci              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
15162306a36Sopenharmony_ci              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
15262306a36Sopenharmony_ci            $ref: /schemas/types.yaml#/definitions/uint32
15362306a36Sopenharmony_ci            enum: [0, 1, 2, 3]
15462306a36Sopenharmony_ci
15562306a36Sopenharmony_ci        required:
15662306a36Sopenharmony_ci          - pinmux
15762306a36Sopenharmony_ci
15862306a36Sopenharmony_ciallOf:
15962306a36Sopenharmony_ci  - $ref: pinctrl.yaml#
16062306a36Sopenharmony_ci
16162306a36Sopenharmony_cirequired:
16262306a36Sopenharmony_ci  - compatible
16362306a36Sopenharmony_ci  - reg
16462306a36Sopenharmony_ci  - reg-names
16562306a36Sopenharmony_ci  - interrupts
16662306a36Sopenharmony_ci  - interrupt-controller
16762306a36Sopenharmony_ci  - '#interrupt-cells'
16862306a36Sopenharmony_ci  - gpio-controller
16962306a36Sopenharmony_ci  - '#gpio-cells'
17062306a36Sopenharmony_ci  - gpio-ranges
17162306a36Sopenharmony_ci
17262306a36Sopenharmony_ciadditionalProperties: false
17362306a36Sopenharmony_ci
17462306a36Sopenharmony_ciexamples:
17562306a36Sopenharmony_ci  - |
17662306a36Sopenharmony_ci    #include <dt-bindings/interrupt-controller/arm-gic.h>
17762306a36Sopenharmony_ci    #include <dt-bindings/interrupt-controller/irq.h>
17862306a36Sopenharmony_ci    #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
17962306a36Sopenharmony_ci
18062306a36Sopenharmony_ci    soc {
18162306a36Sopenharmony_ci        #address-cells = <2>;
18262306a36Sopenharmony_ci        #size-cells = <2>;
18362306a36Sopenharmony_ci
18462306a36Sopenharmony_ci        pio: pinctrl@10005000 {
18562306a36Sopenharmony_ci            compatible = "mediatek,mt6795-pinctrl";
18662306a36Sopenharmony_ci            reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
18762306a36Sopenharmony_ci            reg-names = "base", "eint";
18862306a36Sopenharmony_ci            gpio-controller;
18962306a36Sopenharmony_ci            #gpio-cells = <2>;
19062306a36Sopenharmony_ci            gpio-ranges = <&pio 0 0 196>;
19162306a36Sopenharmony_ci            interrupt-controller;
19262306a36Sopenharmony_ci            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
19362306a36Sopenharmony_ci            #interrupt-cells = <2>;
19462306a36Sopenharmony_ci
19562306a36Sopenharmony_ci            i2c0-pins {
19662306a36Sopenharmony_ci                pins-sda-scl {
19762306a36Sopenharmony_ci                    pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
19862306a36Sopenharmony_ci                             <PINMUX_GPIO46__FUNC_SCL0>;
19962306a36Sopenharmony_ci                };
20062306a36Sopenharmony_ci            };
20162306a36Sopenharmony_ci
20262306a36Sopenharmony_ci            mmc0-pins {
20362306a36Sopenharmony_ci                pins-cmd-dat {
20462306a36Sopenharmony_ci                    pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
20562306a36Sopenharmony_ci                             <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
20662306a36Sopenharmony_ci                             <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
20762306a36Sopenharmony_ci                             <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
20862306a36Sopenharmony_ci                             <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
20962306a36Sopenharmony_ci                             <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
21062306a36Sopenharmony_ci                             <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
21162306a36Sopenharmony_ci                             <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
21262306a36Sopenharmony_ci                             <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
21362306a36Sopenharmony_ci                    input-enable;
21462306a36Sopenharmony_ci                    bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
21562306a36Sopenharmony_ci                };
21662306a36Sopenharmony_ci
21762306a36Sopenharmony_ci                pins-clk {
21862306a36Sopenharmony_ci                    pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
21962306a36Sopenharmony_ci                    bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
22062306a36Sopenharmony_ci                };
22162306a36Sopenharmony_ci
22262306a36Sopenharmony_ci                pins-rst {
22362306a36Sopenharmony_ci                    pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
22462306a36Sopenharmony_ci                    bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
22562306a36Sopenharmony_ci                };
22662306a36Sopenharmony_ci            };
22762306a36Sopenharmony_ci        };
22862306a36Sopenharmony_ci    };
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