162306a36Sopenharmony_ciBroadcom iProc GPIO/PINCONF Controller 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci- compatible: 662306a36Sopenharmony_ci "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that 762306a36Sopenharmony_ci supports full-featured pinctrl and GPIO functions used in various iProc 862306a36Sopenharmony_ci based SoCs 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci May contain an SoC-specific compatibility string to accommodate any 1162306a36Sopenharmony_ci SoC-specific features 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or 1462306a36Sopenharmony_ci "brcm,cygnus-crmu-gpio" for Cygnus SoCs 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support 1762306a36Sopenharmony_ci disabled 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general 2062306a36Sopenharmony_ci pinctrl support completely disabled in this IP block. In Stingray, a 2162306a36Sopenharmony_ci different IP block is used to handle pinctrl related functions 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci- reg: 2462306a36Sopenharmony_ci Define the base and range of the I/O address space that contains SoC 2562306a36Sopenharmony_ciGPIO/PINCONF controller registers 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci- ngpios: 2862306a36Sopenharmony_ci Total number of in-use slots in GPIO controller 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci- #gpio-cells: 3162306a36Sopenharmony_ci Must be two. The first cell is the GPIO pin number (within the 3262306a36Sopenharmony_cicontroller's pin space) and the second cell is used for the following: 3362306a36Sopenharmony_ci bit[0]: polarity (0 for active high and 1 for active low) 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci- gpio-controller: 3662306a36Sopenharmony_ci Specifies that the node is a GPIO controller 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ciOptional properties: 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci- interrupts: 4162306a36Sopenharmony_ci Interrupt ID 4262306a36Sopenharmony_ci 4362306a36Sopenharmony_ci- interrupt-controller: 4462306a36Sopenharmony_ci Specifies that the node is an interrupt controller 4562306a36Sopenharmony_ci 4662306a36Sopenharmony_ci- gpio-ranges: 4762306a36Sopenharmony_ci Specifies the mapping between gpio controller and pin-controllers pins. 4862306a36Sopenharmony_ci This requires 4 fields in cells defined as - 4962306a36Sopenharmony_ci 1. Phandle of pin-controller. 5062306a36Sopenharmony_ci 2. GPIO base pin offset. 5162306a36Sopenharmony_ci 3 Pin-control base pin offset. 5262306a36Sopenharmony_ci 4. number of gpio pins which are linearly mapped from pin base. 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciSupported generic PINCONF properties in child nodes: 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci- pins: 5762306a36Sopenharmony_ci The list of pins (within the controller's own pin space) that properties 5862306a36Sopenharmony_ciin the node apply to. Pin names are "gpio-<pin>" 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci- bias-disable: 6162306a36Sopenharmony_ci Disable pin bias 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci- bias-pull-up: 6462306a36Sopenharmony_ci Enable internal pull up resistor 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci- bias-pull-down: 6762306a36Sopenharmony_ci Enable internal pull down resistor 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ci- drive-strength: 7062306a36Sopenharmony_ci Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ciExample: 7362306a36Sopenharmony_ci gpio_ccm: gpio@1800a000 { 7462306a36Sopenharmony_ci compatible = "brcm,cygnus-ccm-gpio"; 7562306a36Sopenharmony_ci reg = <0x1800a000 0x50>, 7662306a36Sopenharmony_ci <0x0301d164 0x20>; 7762306a36Sopenharmony_ci ngpios = <24>; 7862306a36Sopenharmony_ci #gpio-cells = <2>; 7962306a36Sopenharmony_ci gpio-controller; 8062306a36Sopenharmony_ci interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 8162306a36Sopenharmony_ci interrupt-controller; 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ci touch_pins: touch_pins { 8462306a36Sopenharmony_ci pwr: pwr { 8562306a36Sopenharmony_ci pins = "gpio-0"; 8662306a36Sopenharmony_ci drive-strength = <16>; 8762306a36Sopenharmony_ci }; 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ci event: event { 9062306a36Sopenharmony_ci pins = "gpio-1"; 9162306a36Sopenharmony_ci bias-pull-up; 9262306a36Sopenharmony_ci }; 9362306a36Sopenharmony_ci }; 9462306a36Sopenharmony_ci }; 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci gpio_asiu: gpio@180a5000 { 9762306a36Sopenharmony_ci compatible = "brcm,cygnus-asiu-gpio"; 9862306a36Sopenharmony_ci reg = <0x180a5000 0x668>; 9962306a36Sopenharmony_ci ngpios = <146>; 10062306a36Sopenharmony_ci #gpio-cells = <2>; 10162306a36Sopenharmony_ci gpio-controller; 10262306a36Sopenharmony_ci interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 10362306a36Sopenharmony_ci interrupt-controller; 10462306a36Sopenharmony_ci gpio-ranges = <&pinctrl 0 42 1>, 10562306a36Sopenharmony_ci <&pinctrl 1 44 3>; 10662306a36Sopenharmony_ci }; 10762306a36Sopenharmony_ci 10862306a36Sopenharmony_ci /* 10962306a36Sopenharmony_ci * Touchscreen that uses the CCM GPIO 0 and 1 11062306a36Sopenharmony_ci */ 11162306a36Sopenharmony_ci tsc { 11262306a36Sopenharmony_ci ... 11362306a36Sopenharmony_ci ... 11462306a36Sopenharmony_ci gpio-pwr = <&gpio_ccm 0 0>; 11562306a36Sopenharmony_ci gpio-event = <&gpio_ccm 1 0>; 11662306a36Sopenharmony_ci }; 11762306a36Sopenharmony_ci 11862306a36Sopenharmony_ci /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ 11962306a36Sopenharmony_ci bluetooth { 12062306a36Sopenharmony_ci ... 12162306a36Sopenharmony_ci ... 12262306a36Sopenharmony_ci bcm,rfkill-bank-sel = <&gpio_asiu 5 1> 12362306a36Sopenharmony_ci } 124