162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
362306a36Sopenharmony_ci%YAML 1.2
462306a36Sopenharmony_ci---
562306a36Sopenharmony_ci$id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
662306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
762306a36Sopenharmony_ci
862306a36Sopenharmony_cititle: CPSW Port's Interface Mode Selection PHY
962306a36Sopenharmony_ci
1062306a36Sopenharmony_cimaintainers:
1162306a36Sopenharmony_ci  - Kishon Vijay Abraham I <kishon@ti.com>
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_cidescription: |
1462306a36Sopenharmony_ci  TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
1562306a36Sopenharmony_ci  two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
1662306a36Sopenharmony_ci  The interface mode is selected by configuring the MII mode selection register(s)
1762306a36Sopenharmony_ci  (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
1862306a36Sopenharmony_ci  bit fields placement in SCM are different between SoCs while fields meaning
1962306a36Sopenharmony_ci  is the same.
2062306a36Sopenharmony_ci                                               +--------------+
2162306a36Sopenharmony_ci        +-------------------------------+      |SCM           |
2262306a36Sopenharmony_ci        |                     CPSW      |      |  +---------+ |
2362306a36Sopenharmony_ci        |        +--------------------------------+gmii_sel | |
2462306a36Sopenharmony_ci        |        |                      |      |  +---------+ |
2562306a36Sopenharmony_ci        |   +----v---+     +--------+   |      +--------------+
2662306a36Sopenharmony_ci        |   |Port 1..<--+-->GMII/MII<------->
2762306a36Sopenharmony_ci        |   |        |  |  |        |   |
2862306a36Sopenharmony_ci        |   +--------+  |  +--------+   |
2962306a36Sopenharmony_ci        |               |               |
3062306a36Sopenharmony_ci        |               |  +--------+   |
3162306a36Sopenharmony_ci        |               |  | RMII   <------->
3262306a36Sopenharmony_ci        |               +-->        |   |
3362306a36Sopenharmony_ci        |               |  +--------+   |
3462306a36Sopenharmony_ci        |               |               |
3562306a36Sopenharmony_ci        |               |  +--------+   |
3662306a36Sopenharmony_ci        |               |  | RGMII  <------->
3762306a36Sopenharmony_ci        |               +-->        |   |
3862306a36Sopenharmony_ci        |                  +--------+   |
3962306a36Sopenharmony_ci        +-------------------------------+
4062306a36Sopenharmony_ci
4162306a36Sopenharmony_ci  CPSW Port's Interface Mode Selection PHY describes MII interface mode between
4262306a36Sopenharmony_ci  CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
4362306a36Sopenharmony_ci  |
4462306a36Sopenharmony_ci  CPSW Port's Interface Mode Selection PHY device should defined as child device
4562306a36Sopenharmony_ci  of SCM node (scm_conf) and can be attached to each CPSW port node using standard
4662306a36Sopenharmony_ci  PHY bindings.
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ciproperties:
4962306a36Sopenharmony_ci  compatible:
5062306a36Sopenharmony_ci    enum:
5162306a36Sopenharmony_ci      - ti,am3352-phy-gmii-sel
5262306a36Sopenharmony_ci      - ti,dra7xx-phy-gmii-sel
5362306a36Sopenharmony_ci      - ti,am43xx-phy-gmii-sel
5462306a36Sopenharmony_ci      - ti,dm814-phy-gmii-sel
5562306a36Sopenharmony_ci      - ti,am654-phy-gmii-sel
5662306a36Sopenharmony_ci      - ti,j7200-cpsw5g-phy-gmii-sel
5762306a36Sopenharmony_ci      - ti,j721e-cpsw9g-phy-gmii-sel
5862306a36Sopenharmony_ci      - ti,j784s4-cpsw9g-phy-gmii-sel
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci  reg:
6162306a36Sopenharmony_ci    maxItems: 1
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci  '#phy-cells': true
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci  ti,qsgmii-main-ports:
6662306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32-array
6762306a36Sopenharmony_ci    description: |
6862306a36Sopenharmony_ci      Required only for QSGMII mode. Array to select the port/s for QSGMII
6962306a36Sopenharmony_ci      main mode. The size of the array corresponds to the number of QSGMII
7062306a36Sopenharmony_ci      interfaces and thus, the number of distinct QSGMII main ports,
7162306a36Sopenharmony_ci      supported by the device. If the device supports two QSGMII interfaces
7262306a36Sopenharmony_ci      but only one QSGMII interface is desired, repeat the QSGMII main port
7362306a36Sopenharmony_ci      value corresponding to the QSGMII interface in the array.
7462306a36Sopenharmony_ci    minItems: 1
7562306a36Sopenharmony_ci    maxItems: 2
7662306a36Sopenharmony_ci    items:
7762306a36Sopenharmony_ci      minimum: 1
7862306a36Sopenharmony_ci      maximum: 8
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ciallOf:
8162306a36Sopenharmony_ci  - if:
8262306a36Sopenharmony_ci      properties:
8362306a36Sopenharmony_ci        compatible:
8462306a36Sopenharmony_ci          contains:
8562306a36Sopenharmony_ci            enum:
8662306a36Sopenharmony_ci              - ti,dra7xx-phy-gmii-sel
8762306a36Sopenharmony_ci              - ti,dm814-phy-gmii-sel
8862306a36Sopenharmony_ci              - ti,am654-phy-gmii-sel
8962306a36Sopenharmony_ci              - ti,j7200-cpsw5g-phy-gmii-sel
9062306a36Sopenharmony_ci              - ti,j721e-cpsw9g-phy-gmii-sel
9162306a36Sopenharmony_ci              - ti,j784s4-cpsw9g-phy-gmii-sel
9262306a36Sopenharmony_ci    then:
9362306a36Sopenharmony_ci      properties:
9462306a36Sopenharmony_ci        '#phy-cells':
9562306a36Sopenharmony_ci          const: 1
9662306a36Sopenharmony_ci          description: CPSW port number (starting from 1)
9762306a36Sopenharmony_ci
9862306a36Sopenharmony_ci  - if:
9962306a36Sopenharmony_ci      properties:
10062306a36Sopenharmony_ci        compatible:
10162306a36Sopenharmony_ci          contains:
10262306a36Sopenharmony_ci            enum:
10362306a36Sopenharmony_ci              - ti,j7200-cpsw5g-phy-gmii-sel
10462306a36Sopenharmony_ci    then:
10562306a36Sopenharmony_ci      properties:
10662306a36Sopenharmony_ci        ti,qsgmii-main-ports:
10762306a36Sopenharmony_ci          maxItems: 1
10862306a36Sopenharmony_ci          items:
10962306a36Sopenharmony_ci            minimum: 1
11062306a36Sopenharmony_ci            maximum: 4
11162306a36Sopenharmony_ci
11262306a36Sopenharmony_ci  - if:
11362306a36Sopenharmony_ci      properties:
11462306a36Sopenharmony_ci        compatible:
11562306a36Sopenharmony_ci          contains:
11662306a36Sopenharmony_ci            enum:
11762306a36Sopenharmony_ci              - ti,j721e-cpsw9g-phy-gmii-sel
11862306a36Sopenharmony_ci              - ti,j784s4-cpsw9g-phy-gmii-sel
11962306a36Sopenharmony_ci    then:
12062306a36Sopenharmony_ci      properties:
12162306a36Sopenharmony_ci        ti,qsgmii-main-ports:
12262306a36Sopenharmony_ci          minItems: 2
12362306a36Sopenharmony_ci          maxItems: 2
12462306a36Sopenharmony_ci          items:
12562306a36Sopenharmony_ci            minimum: 1
12662306a36Sopenharmony_ci            maximum: 8
12762306a36Sopenharmony_ci
12862306a36Sopenharmony_ci  - if:
12962306a36Sopenharmony_ci      not:
13062306a36Sopenharmony_ci        properties:
13162306a36Sopenharmony_ci          compatible:
13262306a36Sopenharmony_ci            contains:
13362306a36Sopenharmony_ci              enum:
13462306a36Sopenharmony_ci                - ti,j7200-cpsw5g-phy-gmii-sel
13562306a36Sopenharmony_ci                - ti,j721e-cpsw9g-phy-gmii-sel
13662306a36Sopenharmony_ci                - ti,j784s4-cpsw9g-phy-gmii-sel
13762306a36Sopenharmony_ci    then:
13862306a36Sopenharmony_ci      properties:
13962306a36Sopenharmony_ci        ti,qsgmii-main-ports: false
14062306a36Sopenharmony_ci
14162306a36Sopenharmony_ci  - if:
14262306a36Sopenharmony_ci      properties:
14362306a36Sopenharmony_ci        compatible:
14462306a36Sopenharmony_ci          contains:
14562306a36Sopenharmony_ci            enum:
14662306a36Sopenharmony_ci              - ti,am3352-phy-gmii-sel
14762306a36Sopenharmony_ci              - ti,am43xx-phy-gmii-sel
14862306a36Sopenharmony_ci    then:
14962306a36Sopenharmony_ci      properties:
15062306a36Sopenharmony_ci        '#phy-cells':
15162306a36Sopenharmony_ci          const: 2
15262306a36Sopenharmony_ci          description: |
15362306a36Sopenharmony_ci            - CPSW port number (starting from 1)
15462306a36Sopenharmony_ci            - RMII refclk mode
15562306a36Sopenharmony_ci
15662306a36Sopenharmony_cirequired:
15762306a36Sopenharmony_ci  - compatible
15862306a36Sopenharmony_ci  - reg
15962306a36Sopenharmony_ci  - '#phy-cells'
16062306a36Sopenharmony_ci
16162306a36Sopenharmony_ciadditionalProperties: false
16262306a36Sopenharmony_ci
16362306a36Sopenharmony_ciexamples:
16462306a36Sopenharmony_ci  - |
16562306a36Sopenharmony_ci    phy_gmii_sel: phy@650 {
16662306a36Sopenharmony_ci        compatible = "ti,am3352-phy-gmii-sel";
16762306a36Sopenharmony_ci        reg = <0x650 0x4>;
16862306a36Sopenharmony_ci        #phy-cells = <2>;
16962306a36Sopenharmony_ci    };
170