162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Samsung SoC series UFS PHY 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Alim Akhtar <alim.akhtar@samsung.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciproperties: 1362306a36Sopenharmony_ci "#phy-cells": 1462306a36Sopenharmony_ci const: 0 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci compatible: 1762306a36Sopenharmony_ci enum: 1862306a36Sopenharmony_ci - samsung,exynos7-ufs-phy 1962306a36Sopenharmony_ci - samsung,exynosautov9-ufs-phy 2062306a36Sopenharmony_ci - tesla,fsd-ufs-phy 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci reg: 2362306a36Sopenharmony_ci maxItems: 1 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci reg-names: 2662306a36Sopenharmony_ci items: 2762306a36Sopenharmony_ci - const: phy-pma 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci clocks: 3062306a36Sopenharmony_ci minItems: 1 3162306a36Sopenharmony_ci maxItems: 4 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci clock-names: 3462306a36Sopenharmony_ci minItems: 1 3562306a36Sopenharmony_ci maxItems: 4 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci samsung,pmu-syscon: 3862306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/phandle-array 3962306a36Sopenharmony_ci maxItems: 1 4062306a36Sopenharmony_ci items: 4162306a36Sopenharmony_ci minItems: 1 4262306a36Sopenharmony_ci items: 4362306a36Sopenharmony_ci - description: phandle for PMU system controller interface, used to 4462306a36Sopenharmony_ci control pmu registers bits for ufs m-phy 4562306a36Sopenharmony_ci - description: offset of the pmu control register 4662306a36Sopenharmony_ci description: 4762306a36Sopenharmony_ci It can be phandle/offset pair. The second cell which can represent an 4862306a36Sopenharmony_ci offset is optional. 4962306a36Sopenharmony_ci 5062306a36Sopenharmony_cirequired: 5162306a36Sopenharmony_ci - "#phy-cells" 5262306a36Sopenharmony_ci - compatible 5362306a36Sopenharmony_ci - reg 5462306a36Sopenharmony_ci - reg-names 5562306a36Sopenharmony_ci - clocks 5662306a36Sopenharmony_ci - clock-names 5762306a36Sopenharmony_ci - samsung,pmu-syscon 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ciallOf: 6062306a36Sopenharmony_ci - if: 6162306a36Sopenharmony_ci properties: 6262306a36Sopenharmony_ci compatible: 6362306a36Sopenharmony_ci contains: 6462306a36Sopenharmony_ci const: samsung,exynos7-ufs-phy 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci then: 6762306a36Sopenharmony_ci properties: 6862306a36Sopenharmony_ci clocks: 6962306a36Sopenharmony_ci items: 7062306a36Sopenharmony_ci - description: PLL reference clock 7162306a36Sopenharmony_ci - description: symbol clock for input symbol (rx0-ch0 symbol clock) 7262306a36Sopenharmony_ci - description: symbol clock for input symbol (rx1-ch1 symbol clock) 7362306a36Sopenharmony_ci - description: symbol clock for output symbol (tx0 symbol clock) 7462306a36Sopenharmony_ci 7562306a36Sopenharmony_ci clock-names: 7662306a36Sopenharmony_ci items: 7762306a36Sopenharmony_ci - const: ref_clk 7862306a36Sopenharmony_ci - const: rx1_symbol_clk 7962306a36Sopenharmony_ci - const: rx0_symbol_clk 8062306a36Sopenharmony_ci - const: tx0_symbol_clk 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci else: 8362306a36Sopenharmony_ci properties: 8462306a36Sopenharmony_ci clocks: 8562306a36Sopenharmony_ci items: 8662306a36Sopenharmony_ci - description: PLL reference clock 8762306a36Sopenharmony_ci 8862306a36Sopenharmony_ci clock-names: 8962306a36Sopenharmony_ci items: 9062306a36Sopenharmony_ci - const: ref_clk 9162306a36Sopenharmony_ci 9262306a36Sopenharmony_ciadditionalProperties: false 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ciexamples: 9562306a36Sopenharmony_ci - | 9662306a36Sopenharmony_ci #include <dt-bindings/clock/exynos7-clk.h> 9762306a36Sopenharmony_ci 9862306a36Sopenharmony_ci ufs_phy: ufs-phy@15571800 { 9962306a36Sopenharmony_ci compatible = "samsung,exynos7-ufs-phy"; 10062306a36Sopenharmony_ci reg = <0x15571800 0x240>; 10162306a36Sopenharmony_ci reg-names = "phy-pma"; 10262306a36Sopenharmony_ci samsung,pmu-syscon = <&pmu_system_controller>; 10362306a36Sopenharmony_ci #phy-cells = <0>; 10462306a36Sopenharmony_ci clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, 10562306a36Sopenharmony_ci <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, 10662306a36Sopenharmony_ci <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, 10762306a36Sopenharmony_ci <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; 10862306a36Sopenharmony_ci clock-names = "ref_clk", "rx1_symbol_clk", 10962306a36Sopenharmony_ci "rx0_symbol_clk", "tx0_symbol_clk"; 11062306a36Sopenharmony_ci 11162306a36Sopenharmony_ci }; 11262306a36Sopenharmony_ci... 113