162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Qualcomm PCIe2 PHY controller 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Vinod Koul <vkoul@kernel.org> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: 1362306a36Sopenharmony_ci The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm 1462306a36Sopenharmony_ci platforms. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciproperties: 1762306a36Sopenharmony_ci compatible: 1862306a36Sopenharmony_ci items: 1962306a36Sopenharmony_ci - const: qcom,qcs404-pcie2-phy 2062306a36Sopenharmony_ci - const: qcom,pcie2-phy 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci reg: 2362306a36Sopenharmony_ci items: 2462306a36Sopenharmony_ci - description: PHY register set 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci clocks: 2762306a36Sopenharmony_ci items: 2862306a36Sopenharmony_ci - description: a clock-specifier pair for the "pipe" clock 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ci clock-output-names: 3162306a36Sopenharmony_ci maxItems: 1 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci "#clock-cells": 3462306a36Sopenharmony_ci const: 0 3562306a36Sopenharmony_ci 3662306a36Sopenharmony_ci "#phy-cells": 3762306a36Sopenharmony_ci const: 0 3862306a36Sopenharmony_ci 3962306a36Sopenharmony_ci vdda-vp-supply: 4062306a36Sopenharmony_ci description: low voltage regulator 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci vdda-vph-supply: 4362306a36Sopenharmony_ci description: high voltage regulator 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci resets: 4662306a36Sopenharmony_ci maxItems: 2 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci reset-names: 4962306a36Sopenharmony_ci items: 5062306a36Sopenharmony_ci - const: phy 5162306a36Sopenharmony_ci - const: pipe 5262306a36Sopenharmony_ci 5362306a36Sopenharmony_cirequired: 5462306a36Sopenharmony_ci - compatible 5562306a36Sopenharmony_ci - reg 5662306a36Sopenharmony_ci - clocks 5762306a36Sopenharmony_ci - clock-output-names 5862306a36Sopenharmony_ci - "#clock-cells" 5962306a36Sopenharmony_ci - "#phy-cells" 6062306a36Sopenharmony_ci - vdda-vp-supply 6162306a36Sopenharmony_ci - vdda-vph-supply 6262306a36Sopenharmony_ci - resets 6362306a36Sopenharmony_ci - reset-names 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ciadditionalProperties: false 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ciexamples: 6862306a36Sopenharmony_ci - | 6962306a36Sopenharmony_ci #include <dt-bindings/clock/qcom,gcc-qcs404.h> 7062306a36Sopenharmony_ci phy@7786000 { 7162306a36Sopenharmony_ci compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 7262306a36Sopenharmony_ci reg = <0x07786000 0xb8>; 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 7562306a36Sopenharmony_ci resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 7662306a36Sopenharmony_ci <&gcc GCC_PCIE_0_PIPE_ARES>; 7762306a36Sopenharmony_ci reset-names = "phy", "pipe"; 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci vdda-vp-supply = <&vreg_l3_1p05>; 8062306a36Sopenharmony_ci vdda-vph-supply = <&vreg_l5_1p8>; 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci clock-output-names = "pcie_0_pipe_clk"; 8362306a36Sopenharmony_ci #clock-cells = <0>; 8462306a36Sopenharmony_ci #phy-cells = <0>; 8562306a36Sopenharmony_ci }; 8662306a36Sopenharmony_ci... 87