162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 262306a36Sopenharmony_ci# Copyright (c) 2020 MediaTek 362306a36Sopenharmony_ci%YAML 1.2 462306a36Sopenharmony_ci--- 562306a36Sopenharmony_ci$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml# 662306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 762306a36Sopenharmony_ci 862306a36Sopenharmony_cititle: MediaTek Universal Flash Storage (UFS) M-PHY 962306a36Sopenharmony_ci 1062306a36Sopenharmony_cimaintainers: 1162306a36Sopenharmony_ci - Stanley Chu <stanley.chu@mediatek.com> 1262306a36Sopenharmony_ci - Chunfeng Yun <chunfeng.yun@mediatek.com> 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_cidescription: | 1562306a36Sopenharmony_ci UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 1662306a36Sopenharmony_ci Each UFS M-PHY node should have its own node. 1762306a36Sopenharmony_ci To bind UFS M-PHY with UFS host controller, the controller node should 1862306a36Sopenharmony_ci contain a phandle reference to UFS M-PHY node. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciproperties: 2162306a36Sopenharmony_ci $nodename: 2262306a36Sopenharmony_ci pattern: "^ufs-phy@[0-9a-f]+$" 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ci compatible: 2562306a36Sopenharmony_ci oneOf: 2662306a36Sopenharmony_ci - items: 2762306a36Sopenharmony_ci - enum: 2862306a36Sopenharmony_ci - mediatek,mt8195-ufsphy 2962306a36Sopenharmony_ci - const: mediatek,mt8183-ufsphy 3062306a36Sopenharmony_ci - const: mediatek,mt8183-ufsphy 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci reg: 3362306a36Sopenharmony_ci maxItems: 1 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci clocks: 3662306a36Sopenharmony_ci items: 3762306a36Sopenharmony_ci - description: Unipro core control clock. 3862306a36Sopenharmony_ci - description: M-PHY core control clock. 3962306a36Sopenharmony_ci 4062306a36Sopenharmony_ci clock-names: 4162306a36Sopenharmony_ci items: 4262306a36Sopenharmony_ci - const: unipro 4362306a36Sopenharmony_ci - const: mp 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci "#phy-cells": 4662306a36Sopenharmony_ci const: 0 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_cirequired: 4962306a36Sopenharmony_ci - compatible 5062306a36Sopenharmony_ci - reg 5162306a36Sopenharmony_ci - "#phy-cells" 5262306a36Sopenharmony_ci - clocks 5362306a36Sopenharmony_ci - clock-names 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ciadditionalProperties: false 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ciexamples: 5862306a36Sopenharmony_ci - | 5962306a36Sopenharmony_ci #include <dt-bindings/clock/mt8183-clk.h> 6062306a36Sopenharmony_ci ufsphy: ufs-phy@11fa0000 { 6162306a36Sopenharmony_ci compatible = "mediatek,mt8183-ufsphy"; 6262306a36Sopenharmony_ci reg = <0x11fa0000 0xc000>; 6362306a36Sopenharmony_ci clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 6462306a36Sopenharmony_ci <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>; 6562306a36Sopenharmony_ci clock-names = "unipro", "mp"; 6662306a36Sopenharmony_ci #phy-cells = <0>; 6762306a36Sopenharmony_ci }; 6862306a36Sopenharmony_ci 6962306a36Sopenharmony_ci... 70