162306a36Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: HiSilicon Kirin970 PCIe PHY 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: |+ 1362306a36Sopenharmony_ci Bindings for PCIe PHY on HiSilicon Kirin 970. 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ciproperties: 1662306a36Sopenharmony_ci compatible: 1762306a36Sopenharmony_ci const: hisilicon,hi970-pcie-phy 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci "#phy-cells": 2062306a36Sopenharmony_ci const: 0 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci reg: 2362306a36Sopenharmony_ci maxItems: 1 2462306a36Sopenharmony_ci description: PHY Control registers 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci phy-supply: 2762306a36Sopenharmony_ci description: The PCIe PHY power supply 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci clocks: 3062306a36Sopenharmony_ci items: 3162306a36Sopenharmony_ci - description: PCIe PHY clock 3262306a36Sopenharmony_ci - description: PCIe AUX clock 3362306a36Sopenharmony_ci - description: PCIe APB PHY clock 3462306a36Sopenharmony_ci - description: PCIe APB SYS clock 3562306a36Sopenharmony_ci - description: PCIe ACLK clock 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci clock-names: 3862306a36Sopenharmony_ci items: 3962306a36Sopenharmony_ci - const: phy_ref 4062306a36Sopenharmony_ci - const: aux 4162306a36Sopenharmony_ci - const: apb_phy 4262306a36Sopenharmony_ci - const: apb_sys 4362306a36Sopenharmony_ci - const: aclk 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci hisilicon,eye-diagram-param: 4662306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/uint32-array 4762306a36Sopenharmony_ci description: Eye diagram for phy. 4862306a36Sopenharmony_ci 4962306a36Sopenharmony_cirequired: 5062306a36Sopenharmony_ci - "#phy-cells" 5162306a36Sopenharmony_ci - compatible 5262306a36Sopenharmony_ci - reg 5362306a36Sopenharmony_ci - clocks 5462306a36Sopenharmony_ci - clock-names 5562306a36Sopenharmony_ci - hisilicon,eye-diagram-param 5662306a36Sopenharmony_ci - phy-supply 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ciadditionalProperties: false 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ciexamples: 6162306a36Sopenharmony_ci - | 6262306a36Sopenharmony_ci #include <dt-bindings/clock/hi3670-clock.h> 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci soc { 6562306a36Sopenharmony_ci #address-cells = <2>; 6662306a36Sopenharmony_ci #size-cells = <2>; 6762306a36Sopenharmony_ci pcie_phy: pcie-phy@fc000000 { 6862306a36Sopenharmony_ci compatible = "hisilicon,hi970-pcie-phy"; 6962306a36Sopenharmony_ci reg = <0x0 0xfc000000 0x0 0x80000>; 7062306a36Sopenharmony_ci #phy-cells = <0>; 7162306a36Sopenharmony_ci phy-supply = <&ldo33>; 7262306a36Sopenharmony_ci clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, 7362306a36Sopenharmony_ci <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, 7462306a36Sopenharmony_ci <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, 7562306a36Sopenharmony_ci <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, 7662306a36Sopenharmony_ci <&crg_ctrl HI3670_ACLK_GATE_PCIE>; 7762306a36Sopenharmony_ci clock-names = "phy_ref", "aux", 7862306a36Sopenharmony_ci "apb_phy", "apb_sys", "aclk"; 7962306a36Sopenharmony_ci hisilicon,eye-diagram-param = <0xffffffff 0xffffffff 8062306a36Sopenharmony_ci 0xffffffff 0xffffffff 0xffffffff>; 8162306a36Sopenharmony_ci }; 8262306a36Sopenharmony_ci }; 83