162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: CTU CAN FD Open-source IP Core
862306a36Sopenharmony_ci
962306a36Sopenharmony_cidescription: |
1062306a36Sopenharmony_ci  Open-source CAN FD IP core developed at the Czech Technical University in Prague
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci  The core sources and documentation on project page
1362306a36Sopenharmony_ci    [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
1462306a36Sopenharmony_ci    [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci  Integration in Xilinx Zynq SoC based system together with
1762306a36Sopenharmony_ci  OpenCores SJA1000 compatible controllers
1862306a36Sopenharmony_ci    [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
1962306a36Sopenharmony_ci  Martin Jerabek dimploma thesis with integration and testing
2062306a36Sopenharmony_ci  framework description
2162306a36Sopenharmony_ci    [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf
2262306a36Sopenharmony_ci
2362306a36Sopenharmony_cimaintainers:
2462306a36Sopenharmony_ci  - Pavel Pisa <pisa@cmp.felk.cvut.cz>
2562306a36Sopenharmony_ci  - Ondrej Ille <ondrej.ille@gmail.com>
2662306a36Sopenharmony_ci  - Martin Jerabek <martin.jerabek01@gmail.com>
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ciallOf:
2962306a36Sopenharmony_ci  - $ref: can-controller.yaml#
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ciproperties:
3262306a36Sopenharmony_ci  compatible:
3362306a36Sopenharmony_ci    oneOf:
3462306a36Sopenharmony_ci      - items:
3562306a36Sopenharmony_ci          - const: ctu,ctucanfd-2
3662306a36Sopenharmony_ci          - const: ctu,ctucanfd
3762306a36Sopenharmony_ci      - const: ctu,ctucanfd
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci  reg:
4062306a36Sopenharmony_ci    maxItems: 1
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci  interrupts:
4362306a36Sopenharmony_ci    maxItems: 1
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci  clocks:
4662306a36Sopenharmony_ci    description: |
4762306a36Sopenharmony_ci      phandle of reference clock (100 MHz is appropriate
4862306a36Sopenharmony_ci      for FPGA implementation on Zynq-7000 system).
4962306a36Sopenharmony_ci    maxItems: 1
5062306a36Sopenharmony_ci
5162306a36Sopenharmony_cirequired:
5262306a36Sopenharmony_ci  - compatible
5362306a36Sopenharmony_ci  - reg
5462306a36Sopenharmony_ci  - interrupts
5562306a36Sopenharmony_ci  - clocks
5662306a36Sopenharmony_ci
5762306a36Sopenharmony_ciadditionalProperties: false
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ciexamples:
6062306a36Sopenharmony_ci  - |
6162306a36Sopenharmony_ci    ctu_can_fd_0: can@43c30000 {
6262306a36Sopenharmony_ci      compatible = "ctu,ctucanfd";
6362306a36Sopenharmony_ci      interrupts = <0 30 4>;
6462306a36Sopenharmony_ci      clocks = <&clkc 15>;
6562306a36Sopenharmony_ci      reg = <0x43c30000 0x10000>;
6662306a36Sopenharmony_ci    };
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