162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
262306a36Sopenharmony_ci%YAML 1.2
362306a36Sopenharmony_ci---
462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml#
662306a36Sopenharmony_ci
762306a36Sopenharmony_cititle: Raw NAND Chip Common Properties
862306a36Sopenharmony_ci
962306a36Sopenharmony_cimaintainers:
1062306a36Sopenharmony_ci  - Miquel Raynal <miquel.raynal@bootlin.com>
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ciallOf:
1362306a36Sopenharmony_ci  - $ref: nand-chip.yaml#
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_cidescription: |
1662306a36Sopenharmony_ci  The ECC strength and ECC step size properties define the user
1762306a36Sopenharmony_ci  desires in terms of correction capability of a controller. Together,
1862306a36Sopenharmony_ci  they request the ECC engine to correct {strength} bit errors per
1962306a36Sopenharmony_ci  {size} bytes for a particular raw NAND chip.
2062306a36Sopenharmony_ci
2162306a36Sopenharmony_ci  The interpretation of these parameters is implementation-defined, so
2262306a36Sopenharmony_ci  not all implementations must support all possible
2362306a36Sopenharmony_ci  combinations. However, implementations are encouraged to further
2462306a36Sopenharmony_ci  specify the value(s) they support.
2562306a36Sopenharmony_ci
2662306a36Sopenharmony_ciproperties:
2762306a36Sopenharmony_ci  $nodename:
2862306a36Sopenharmony_ci    pattern: "^nand@[a-f0-9]$"
2962306a36Sopenharmony_ci
3062306a36Sopenharmony_ci  reg:
3162306a36Sopenharmony_ci    description:
3262306a36Sopenharmony_ci      Contains the chip-select IDs.
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci  nand-ecc-placement:
3562306a36Sopenharmony_ci    description:
3662306a36Sopenharmony_ci      Location of the ECC bytes. This location is unknown by default
3762306a36Sopenharmony_ci      but can be explicitly set to "oob", if all ECC bytes are
3862306a36Sopenharmony_ci      known to be stored in the OOB area, or "interleaved" if ECC
3962306a36Sopenharmony_ci      bytes will be interleaved with regular data in the main area.
4062306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/string
4162306a36Sopenharmony_ci    enum: [ oob, interleaved ]
4262306a36Sopenharmony_ci    deprecated: true
4362306a36Sopenharmony_ci
4462306a36Sopenharmony_ci  nand-ecc-mode:
4562306a36Sopenharmony_ci    description:
4662306a36Sopenharmony_ci      Legacy ECC configuration mixing the ECC engine choice and
4762306a36Sopenharmony_ci      configuration.
4862306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/string
4962306a36Sopenharmony_ci    enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]
5062306a36Sopenharmony_ci    deprecated: true
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci  nand-bus-width:
5362306a36Sopenharmony_ci    description:
5462306a36Sopenharmony_ci      Bus width to the NAND chip
5562306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32
5662306a36Sopenharmony_ci    enum: [8, 16]
5762306a36Sopenharmony_ci    default: 8
5862306a36Sopenharmony_ci
5962306a36Sopenharmony_ci  nand-on-flash-bbt:
6062306a36Sopenharmony_ci    description:
6162306a36Sopenharmony_ci      With this property, the OS will search the device for a Bad
6262306a36Sopenharmony_ci      Block Table (BBT). If not found, it will create one, reserve
6362306a36Sopenharmony_ci      a few blocks at the end of the device to store it and update
6462306a36Sopenharmony_ci      it as the device ages. Otherwise, the out-of-band area of a
6562306a36Sopenharmony_ci      few pages of all the blocks will be scanned at boot time to
6662306a36Sopenharmony_ci      find Bad Block Markers (BBM). These markers will help to
6762306a36Sopenharmony_ci      build a volatile BBT in RAM.
6862306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/flag
6962306a36Sopenharmony_ci
7062306a36Sopenharmony_ci  nand-ecc-maximize:
7162306a36Sopenharmony_ci    description:
7262306a36Sopenharmony_ci      Whether or not the ECC strength should be maximized. The
7362306a36Sopenharmony_ci      maximum ECC strength is both controller and chip
7462306a36Sopenharmony_ci      dependent. The ECC engine has to select the ECC config
7562306a36Sopenharmony_ci      providing the best strength and taking the OOB area size
7662306a36Sopenharmony_ci      constraint into account. This is particularly useful when
7762306a36Sopenharmony_ci      only the in-band area is used by the upper layers, and you
7862306a36Sopenharmony_ci      want to make your NAND as reliable as possible.
7962306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/flag
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_ci  nand-is-boot-medium:
8262306a36Sopenharmony_ci    description:
8362306a36Sopenharmony_ci      Whether or not the NAND chip is a boot medium. Drivers might
8462306a36Sopenharmony_ci      use this information to select ECC algorithms supported by
8562306a36Sopenharmony_ci      the boot ROM or similar restrictions.
8662306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/flag
8762306a36Sopenharmony_ci
8862306a36Sopenharmony_ci  nand-rb:
8962306a36Sopenharmony_ci    description:
9062306a36Sopenharmony_ci      Contains the native Ready/Busy IDs.
9162306a36Sopenharmony_ci    $ref: /schemas/types.yaml#/definitions/uint32-array
9262306a36Sopenharmony_ci
9362306a36Sopenharmony_ci  rb-gpios:
9462306a36Sopenharmony_ci    description:
9562306a36Sopenharmony_ci      Contains one or more GPIO descriptor (the numper of descriptor
9662306a36Sopenharmony_ci      depends on the number of R/B pins exposed by the flash) for the
9762306a36Sopenharmony_ci      Ready/Busy pins. Active state refers to the NAND ready state and
9862306a36Sopenharmony_ci      should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
9962306a36Sopenharmony_ci
10062306a36Sopenharmony_ci  wp-gpios:
10162306a36Sopenharmony_ci    description:
10262306a36Sopenharmony_ci      Contains one GPIO descriptor for the Write Protect pin.
10362306a36Sopenharmony_ci      Active state refers to the NAND Write Protect state and should be
10462306a36Sopenharmony_ci      set to GPIOD_ACTIVE_LOW unless the signal is inverted.
10562306a36Sopenharmony_ci    maxItems: 1
10662306a36Sopenharmony_ci
10762306a36Sopenharmony_cirequired:
10862306a36Sopenharmony_ci  - reg
10962306a36Sopenharmony_ci
11062306a36Sopenharmony_ci# This is a generic file other binding inherit from and extend
11162306a36Sopenharmony_ciadditionalProperties: true
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