162306a36Sopenharmony_ciNVIDIA Tegra NAND Flash controller 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- compatible: Must be one of: 562306a36Sopenharmony_ci - "nvidia,tegra20-nand" 662306a36Sopenharmony_ci- reg: MMIO address range 762306a36Sopenharmony_ci- interrupts: interrupt output of the NFC controller 862306a36Sopenharmony_ci- clocks: Must contain an entry for each entry in clock-names. 962306a36Sopenharmony_ci See ../clocks/clock-bindings.txt for details. 1062306a36Sopenharmony_ci- clock-names: Must include the following entries: 1162306a36Sopenharmony_ci - nand 1262306a36Sopenharmony_ci- resets: Must contain an entry for each entry in reset-names. 1362306a36Sopenharmony_ci See ../reset/reset.txt for details. 1462306a36Sopenharmony_ci- reset-names: Must include the following entries: 1562306a36Sopenharmony_ci - nand 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ciOptional children nodes: 1862306a36Sopenharmony_ciIndividual NAND chips are children of the NAND controller node. Currently 1962306a36Sopenharmony_cionly one NAND chip supported. 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ciRequired children node properties: 2262306a36Sopenharmony_ci- reg: An integer ranging from 1 to 6 representing the CS line to use. 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciOptional children node properties: 2562306a36Sopenharmony_ci- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only 2662306a36Sopenharmony_ci "hw" is supported. 2762306a36Sopenharmony_ci- nand-ecc-algo: string, algorithm of NAND ECC. 2862306a36Sopenharmony_ci Supported values with "hw" ECC mode are: "rs", "bch". 2962306a36Sopenharmony_ci- nand-bus-width : See nand-controller.yaml 3062306a36Sopenharmony_ci- nand-on-flash-bbt: See nand-controller.yaml 3162306a36Sopenharmony_ci- nand-ecc-strength: integer representing the number of bits to correct 3262306a36Sopenharmony_ci per ECC step (always 512). Supported strength using HW ECC 3362306a36Sopenharmony_ci modes are: 3462306a36Sopenharmony_ci - RS: 4, 6, 8 3562306a36Sopenharmony_ci - BCH: 4, 8, 14, 16 3662306a36Sopenharmony_ci- nand-ecc-maximize: See nand-controller.yaml 3762306a36Sopenharmony_ci- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM 3862306a36Sopenharmony_ci are chosen. 3962306a36Sopenharmony_ci- wp-gpios: GPIO specifier for the write protect pin. 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ciOptional child node of NAND chip nodes: 4262306a36Sopenharmony_ciPartitions: see partition.txt 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci Example: 4562306a36Sopenharmony_ci nand-controller@70008000 { 4662306a36Sopenharmony_ci compatible = "nvidia,tegra20-nand"; 4762306a36Sopenharmony_ci reg = <0x70008000 0x100>; 4862306a36Sopenharmony_ci interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 4962306a36Sopenharmony_ci clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 5062306a36Sopenharmony_ci clock-names = "nand"; 5162306a36Sopenharmony_ci resets = <&tegra_car 13>; 5262306a36Sopenharmony_ci reset-names = "nand"; 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci nand@0 { 5562306a36Sopenharmony_ci reg = <0>; 5662306a36Sopenharmony_ci #address-cells = <1>; 5762306a36Sopenharmony_ci #size-cells = <1>; 5862306a36Sopenharmony_ci nand-bus-width = <8>; 5962306a36Sopenharmony_ci nand-on-flash-bbt; 6062306a36Sopenharmony_ci nand-ecc-algo = "bch"; 6162306a36Sopenharmony_ci nand-ecc-strength = <8>; 6262306a36Sopenharmony_ci wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 6362306a36Sopenharmony_ci }; 6462306a36Sopenharmony_ci }; 65