162306a36Sopenharmony_ciMacronix Raw NAND Controller Device Tree Bindings 262306a36Sopenharmony_ci------------------------------------------------- 362306a36Sopenharmony_ci 462306a36Sopenharmony_ciRequired properties: 562306a36Sopenharmony_ci- compatible: should be "mxic,multi-itfc-v009-nand-controller" 662306a36Sopenharmony_ci- reg: should contain 1 entry for the registers 762306a36Sopenharmony_ci- #address-cells: should be set to 1 862306a36Sopenharmony_ci- #size-cells: should be set to 0 962306a36Sopenharmony_ci- interrupts: interrupt line connected to this raw NAND controller 1062306a36Sopenharmony_ci- clock-names: should contain "ps", "send" and "send_dly" 1162306a36Sopenharmony_ci- clocks: should contain 3 phandles for the "ps", "send" and 1262306a36Sopenharmony_ci "send_dly" clocks 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciChildren nodes: 1562306a36Sopenharmony_ci- children nodes represent the available NAND chips. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ciSee Documentation/devicetree/bindings/mtd/nand-controller.yaml 1862306a36Sopenharmony_cifor more details on generic bindings. 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciExample: 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci nand: nand-controller@43c30000 { 2362306a36Sopenharmony_ci compatible = "mxic,multi-itfc-v009-nand-controller"; 2462306a36Sopenharmony_ci reg = <0x43c30000 0x10000>; 2562306a36Sopenharmony_ci #address-cells = <1>; 2662306a36Sopenharmony_ci #size-cells = <0>; 2762306a36Sopenharmony_ci interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; 2862306a36Sopenharmony_ci clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; 2962306a36Sopenharmony_ci clock-names = "send", "send_dly", "ps"; 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci nand@0 { 3262306a36Sopenharmony_ci reg = <0>; 3362306a36Sopenharmony_ci nand-ecc-mode = "soft"; 3462306a36Sopenharmony_ci nand-ecc-algo = "bch"; 3562306a36Sopenharmony_ci }; 3662306a36Sopenharmony_ci }; 37