162306a36Sopenharmony_ciFreescale Localbus UPM programmed to work with NAND flash 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- compatible : "fsl,upm-nand". 562306a36Sopenharmony_ci- reg : should specify localbus chip select and size used for the chip. 662306a36Sopenharmony_ci- fsl,upm-addr-offset : UPM pattern offset for the address latch. 762306a36Sopenharmony_ci- fsl,upm-cmd-offset : UPM pattern offset for the command latch. 862306a36Sopenharmony_ci 962306a36Sopenharmony_ciOptional properties: 1062306a36Sopenharmony_ci- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support. 1162306a36Sopenharmony_ci The corresponding address lines are used to select the chip. 1262306a36Sopenharmony_ci- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins 1362306a36Sopenharmony_ci (R/B#). For multi-chip devices, "n" GPIO definitions are required 1462306a36Sopenharmony_ci according to the number of chips. 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ciDeprecated properties: 1762306a36Sopenharmony_ci- fsl,upm-wait-flags : add chip-dependent short delays after running the 1862306a36Sopenharmony_ci UPM pattern (0x1), after writing a data byte (0x2) or after 1962306a36Sopenharmony_ci writing out a buffer (0x4). 2062306a36Sopenharmony_ci- chip-delay : chip dependent delay for transferring data from array to 2162306a36Sopenharmony_ci read registers (tR). Required if property "gpios" is not used 2262306a36Sopenharmony_ci (R/B# pins not connected). 2362306a36Sopenharmony_ci 2462306a36Sopenharmony_ciEach flash chip described may optionally contain additional sub-nodes 2562306a36Sopenharmony_cidescribing partitions of the address space. See partition.txt for more 2662306a36Sopenharmony_cidetail. 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ciExamples: 2962306a36Sopenharmony_ci 3062306a36Sopenharmony_ciupm@1,0 { 3162306a36Sopenharmony_ci compatible = "fsl,upm-nand"; 3262306a36Sopenharmony_ci reg = <1 0 1>; 3362306a36Sopenharmony_ci fsl,upm-addr-offset = <16>; 3462306a36Sopenharmony_ci fsl,upm-cmd-offset = <8>; 3562306a36Sopenharmony_ci gpios = <&qe_pio_e 18 0>; 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci flash { 3862306a36Sopenharmony_ci #address-cells = <1>; 3962306a36Sopenharmony_ci #size-cells = <1>; 4062306a36Sopenharmony_ci compatible = "..."; 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci partition@0 { 4362306a36Sopenharmony_ci ... 4462306a36Sopenharmony_ci }; 4562306a36Sopenharmony_ci }; 4662306a36Sopenharmony_ci}; 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ciupm@3,0 { 4962306a36Sopenharmony_ci #address-cells = <0>; 5062306a36Sopenharmony_ci #size-cells = <0>; 5162306a36Sopenharmony_ci compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand"; 5262306a36Sopenharmony_ci reg = <3 0x0 0x800>; 5362306a36Sopenharmony_ci fsl,upm-addr-offset = <0x10>; 5462306a36Sopenharmony_ci fsl,upm-cmd-offset = <0x08>; 5562306a36Sopenharmony_ci /* Multi-chip NAND device */ 5662306a36Sopenharmony_ci fsl,upm-addr-line-cs-offsets = <0x0 0x200>; 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci nand@0 { 5962306a36Sopenharmony_ci #address-cells = <1>; 6062306a36Sopenharmony_ci #size-cells = <1>; 6162306a36Sopenharmony_ci 6262306a36Sopenharmony_ci partition@0 { 6362306a36Sopenharmony_ci label = "fs"; 6462306a36Sopenharmony_ci reg = <0x00000000 0x10000000>; 6562306a36Sopenharmony_ci }; 6662306a36Sopenharmony_ci }; 6762306a36Sopenharmony_ci}; 68