162306a36Sopenharmony_ciLantiq XWAY SoC FPI BUS binding
262306a36Sopenharmony_ci============================
362306a36Sopenharmony_ci
462306a36Sopenharmony_ci
562306a36Sopenharmony_ci-------------------------------------------------------------------------------
662306a36Sopenharmony_ciRequired properties:
762306a36Sopenharmony_ci- compatible			: Should be one of
862306a36Sopenharmony_ci					"lantiq,xrx200-fpi"
962306a36Sopenharmony_ci- reg				: The address and length of the XBAR
1062306a36Sopenharmony_ci				  configuration register.
1162306a36Sopenharmony_ci				  Address and length of the FPI bus itself.
1262306a36Sopenharmony_ci- lantiq,rcu			: A phandle to the RCU syscon
1362306a36Sopenharmony_ci- lantiq,offset-endianness	: Offset of the endianness configuration
1462306a36Sopenharmony_ci				  register
1562306a36Sopenharmony_ci
1662306a36Sopenharmony_ci-------------------------------------------------------------------------------
1762306a36Sopenharmony_ciExample for the FPI on the xrx200 SoCs:
1862306a36Sopenharmony_ci	fpi@10000000 {
1962306a36Sopenharmony_ci		compatible = "lantiq,xrx200-fpi";
2062306a36Sopenharmony_ci		ranges = <0x0 0x10000000 0xf000000>;
2162306a36Sopenharmony_ci		reg =	<0x1f400000 0x1000>,
2262306a36Sopenharmony_ci			<0x10000000 0xf000000>;
2362306a36Sopenharmony_ci		lantiq,rcu = <&rcu0>;
2462306a36Sopenharmony_ci		lantiq,offset-endianness = <0x4c>;
2562306a36Sopenharmony_ci		#address-cells = <1>;
2662306a36Sopenharmony_ci		#size-cells = <1>;
2762306a36Sopenharmony_ci
2862306a36Sopenharmony_ci		gptu@e100a00 {
2962306a36Sopenharmony_ci			......
3062306a36Sopenharmony_ci		};
3162306a36Sopenharmony_ci	};
32