162306a36Sopenharmony_ci# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 262306a36Sopenharmony_ci%YAML 1.2 362306a36Sopenharmony_ci--- 462306a36Sopenharmony_ci$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml# 562306a36Sopenharmony_ci$schema: http://devicetree.org/meta-schemas/core.yaml# 662306a36Sopenharmony_ci 762306a36Sopenharmony_cititle: Renesas R-Car Fine Display Processor (FDP1) 862306a36Sopenharmony_ci 962306a36Sopenharmony_cimaintainers: 1062306a36Sopenharmony_ci - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_cidescription: 1362306a36Sopenharmony_ci The FDP1 is a de-interlacing module which converts interlaced video to 1462306a36Sopenharmony_ci progressive video. It is capable of performing pixel format conversion 1562306a36Sopenharmony_ci between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are 1662306a36Sopenharmony_ci supported as an input to the module. 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ciproperties: 1962306a36Sopenharmony_ci compatible: 2062306a36Sopenharmony_ci enum: 2162306a36Sopenharmony_ci - renesas,fdp1 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci reg: 2462306a36Sopenharmony_ci maxItems: 1 2562306a36Sopenharmony_ci 2662306a36Sopenharmony_ci interrupts: 2762306a36Sopenharmony_ci maxItems: 1 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci clocks: 3062306a36Sopenharmony_ci maxItems: 1 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci power-domains: 3362306a36Sopenharmony_ci maxItems: 1 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci resets: 3662306a36Sopenharmony_ci maxItems: 1 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci renesas,fcp: 3962306a36Sopenharmony_ci $ref: /schemas/types.yaml#/definitions/phandle 4062306a36Sopenharmony_ci description: 4162306a36Sopenharmony_ci A phandle referencing the FCP that handles memory accesses for the FDP1. 4262306a36Sopenharmony_ci Not allowed on R-Car Gen2, mandatory on R-Car Gen3. 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_cirequired: 4562306a36Sopenharmony_ci - compatible 4662306a36Sopenharmony_ci - reg 4762306a36Sopenharmony_ci - interrupts 4862306a36Sopenharmony_ci - clocks 4962306a36Sopenharmony_ci - power-domains 5062306a36Sopenharmony_ci - resets 5162306a36Sopenharmony_ci 5262306a36Sopenharmony_ciadditionalProperties: false 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ciexamples: 5562306a36Sopenharmony_ci - | 5662306a36Sopenharmony_ci #include <dt-bindings/clock/renesas-cpg-mssr.h> 5762306a36Sopenharmony_ci #include <dt-bindings/interrupt-controller/arm-gic.h> 5862306a36Sopenharmony_ci #include <dt-bindings/power/r8a7795-sysc.h> 5962306a36Sopenharmony_ci 6062306a36Sopenharmony_ci fdp1@fe940000 { 6162306a36Sopenharmony_ci compatible = "renesas,fdp1"; 6262306a36Sopenharmony_ci reg = <0xfe940000 0x2400>; 6362306a36Sopenharmony_ci interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 6462306a36Sopenharmony_ci clocks = <&cpg CPG_MOD 119>; 6562306a36Sopenharmony_ci power-domains = <&sysc R8A7795_PD_A3VP>; 6662306a36Sopenharmony_ci resets = <&cpg 119>; 6762306a36Sopenharmony_ci renesas,fcp = <&fcpf0>; 6862306a36Sopenharmony_ci }; 6962306a36Sopenharmony_ci... 70