162306a36Sopenharmony_ciRockchip mailbox 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciThe Rockchip mailbox is used by the Rockchip CPU cores to communicate 462306a36Sopenharmony_cirequests to MCU processor. 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciRefer to ./mailbox.txt for generic information about mailbox device-tree 762306a36Sopenharmony_cibindings. 862306a36Sopenharmony_ci 962306a36Sopenharmony_ciRequired properties: 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci - compatible: should be one of the following. 1262306a36Sopenharmony_ci - "rockchip,rk3368-mbox" for rk3368 1362306a36Sopenharmony_ci - reg: physical base address of the controller and length of memory mapped 1462306a36Sopenharmony_ci region. 1562306a36Sopenharmony_ci - interrupts: The interrupt number to the cpu. The interrupt specifier format 1662306a36Sopenharmony_ci depends on the interrupt controller. 1762306a36Sopenharmony_ci - #mbox-cells: Common mailbox binding property to identify the number 1862306a36Sopenharmony_ci of cells required for the mailbox specifier. Should be 1 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ciExample: 2162306a36Sopenharmony_ci-------- 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci/* RK3368 */ 2462306a36Sopenharmony_cimbox: mbox@ff6b0000 { 2562306a36Sopenharmony_ci compatible = "rockchip,rk3368-mailbox"; 2662306a36Sopenharmony_ci reg = <0x0 0xff6b0000 0x0 0x1000>, 2762306a36Sopenharmony_ci interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2862306a36Sopenharmony_ci <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2962306a36Sopenharmony_ci <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3062306a36Sopenharmony_ci <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 3162306a36Sopenharmony_ci #mbox-cells = <1>; 3262306a36Sopenharmony_ci}; 33