162306a36Sopenharmony_ciThe PDC driver manages data transfer to and from various offload engines 262306a36Sopenharmony_cion some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is 362306a36Sopenharmony_cione device tree entry per block. On some chips, the PDC functionality is 462306a36Sopenharmony_cihandled by the FA2 (Northstar Plus). 562306a36Sopenharmony_ci 662306a36Sopenharmony_ciRequired properties: 762306a36Sopenharmony_ci- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 862306a36Sopenharmony_ci FA2/Northstar Plus. 962306a36Sopenharmony_ci- reg: Should contain PDC registers location and length. 1062306a36Sopenharmony_ci- interrupts: Should contain the IRQ line for the PDC. 1162306a36Sopenharmony_ci- #mbox-cells: 1 1262306a36Sopenharmony_ci- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ciOptional properties: 1562306a36Sopenharmony_ci- brcm,use-bcm-hdr: present if a BCM header precedes each frame. 1662306a36Sopenharmony_ci 1762306a36Sopenharmony_ciExample: 1862306a36Sopenharmony_ci pdc0: iproc-pdc0@612c0000 { 1962306a36Sopenharmony_ci compatible = "brcm,iproc-pdc-mbox"; 2062306a36Sopenharmony_ci reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ 2162306a36Sopenharmony_ci interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2262306a36Sopenharmony_ci #mbox-cells = <1>; /* one cell per mailbox channel */ 2362306a36Sopenharmony_ci brcm,rx-status-len = <32>; 2462306a36Sopenharmony_ci brcm,use-bcm-hdr; 2562306a36Sopenharmony_ci }; 26