162306a36Sopenharmony_ciNVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) 262306a36Sopenharmony_ci 362306a36Sopenharmony_ciRequired properties: 462306a36Sopenharmony_ci- compatible : "nvidia,tegra30-smmu" 562306a36Sopenharmony_ci- reg : Should contain 3 register banks(address and length) for each 662306a36Sopenharmony_ci of the SMMU register blocks. 762306a36Sopenharmony_ci- interrupts : Should contain MC General interrupt. 862306a36Sopenharmony_ci- nvidia,#asids : # of ASIDs 962306a36Sopenharmony_ci- dma-window : IOVA start address and length. 1062306a36Sopenharmony_ci- nvidia,ahb : phandle to the ahb bus connected to SMMU. 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ciExample: 1362306a36Sopenharmony_ci smmu { 1462306a36Sopenharmony_ci compatible = "nvidia,tegra30-smmu"; 1562306a36Sopenharmony_ci reg = <0x7000f010 0x02c 1662306a36Sopenharmony_ci 0x7000f1f0 0x010 1762306a36Sopenharmony_ci 0x7000f228 0x05c>; 1862306a36Sopenharmony_ci nvidia,#asids = <4>; /* # of ASIDs */ 1962306a36Sopenharmony_ci dma-window = <0 0x40000000>; /* IOVA start & length */ 2062306a36Sopenharmony_ci nvidia,ahb = <&ahb>; 2162306a36Sopenharmony_ci }; 22